Engineering Change Order or ECO in VLSI is the practice of introducing logic directly into the gate level netlist corresponding to a change that happens in the RTL. This owes to design mistake repairs or a change request from the customer.
Engineering Change Order or ECO in VLSI is used to accommodate last-minute design revisions. ECO is widely used in the industry since it saves money and time. When we talk about ECOs in VLSI, we’re referring to ECOs in the layout. So, on the gate level netlist, you usually start with an ECO. Before passing it on to the layout, the designer must alter the gate-level netlist, make the identical changes in RTL, and then pass all verifications. Before you start changing your layout, make sure the ECO in VLSI physical design passes formal and functional verification.
Flow of ECO in VLSI:
The tapeout is the final stage of the physical design process. And it provides a great deal of mental relief to the whole project team. Tapeout refers to the process of transferring a clean layout file in the form of GDSII/OASIS to the foundry for fabrication after passing all of the foundry’s tests. However, there may be many sleepless nights ahead of the tapeout while physical design engineers/signoff engineers work to close the design. There are several sign offs, such as physical signoff, timing signoff, and IR signoff, that must be completed before the blueprint can be sent to the foundry. And the ECO (Engineering Change Order) phase comes into role when all of these final accomplishments are made. In comparison to a full chip respin, ECO is more favored since it saves time and money.
What Happens During The ECO Phase in VLSI?
ECO in VLSI refers to the phase of the physical design stage when engineers seal all of the signoff checks that were left open during the PnR stage. Timing, DRC, and IR are usually closable in PnR, but the ultimate closing is done in the ECO phase. During ECO in VLSI, engineers complete the PnR implementation operations and resolve any outstanding issues using solely the ECO. However, before approaching the ECO stage, they must have solid time and DRC statistics, as well as assurance that all open concerns would be resolved in the ECO stage. They focus on closing each outstanding problem during the ECO phase, generating ECO files and slowly implementing them on the PnR tool.
What is The ECO Cycle And How Does It Function?
Engineers do several analyses one by one for each check that has to be closed but is not completed until the PnR stage in the ECO cycle. There are specialist signoff tools that assist them in analyzing the problem and recommending improvements to do, in order to resolve it. An eco file is created to record the requested modification.
After generating the ECO file for the fixes, they start applying it to the PnR database where the analysis was done. They preserve the changed database after ECO file implementation and take it forward for the next ECO generation and implementation. And they repeat the ECO cycle for each open problem, closing them one by one.
In a shell, Each ECO Cycle Includes The Following Phases:
- An investigation of a problem using the most recent database
- ECO generation to address the problem
- ECO implementation on the database that was studied
- After ECO deployment, save the database for the next ECO cycle.
Conclusion
With the growing size and complexity of SOC logic, as well as the development of complicated logic optimization techniques during synthesis, and the lack of a solid ECO flow/tool, implementing ECOs in VLSI physical design is becoming increasingly problematic. Although there are solutions available on the market to assist with ECO adoption, they are generally unstable and unreliable.
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