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ChipEdge now offers Integrated Internship courses for Students / Freshers (Enquire now).
Learn ASIC verification course, the most in-demand skill set with high number of jobs in VLSI. The course is Designed & delivered by Verification Experts from VLSI Industry, with Live Online Classes on Weekends.
27th May 2023
4 Months
Live Online Classess
Design Verification (DV) is also called RTL / Functional Verification, which involves testing the Design for Functionality. ASIC Verification in VLSI is similar to testing work in the software industry. In any VLSI Project, the number of Design Verification Engineers is more than other skill sets. Hence a number of job opportunities is more for Verification Engineers. Trained DV Engineers are on demand most of the time.
DV Engineers exhaustively test the design (RTL Code) for functionality and closely work with RTL Design Engineers to get the bugs fixed.
ASIC Design and Verification Course comprehensively covers digital design, Verilog for verification with multiple examples & projects, System Verilog & UVM along with labs & projects. 2 to 3 protocols will be covered during training and in the ASIC verification online course.
ASIC Verification Course is designed and delivered by practicing experts in Verification, as per the industry requirements. Importance is given to cover the concepts and methodology along with a good emphasis on hands-on training. 60% of the course time is allocated to the guided lab sessions and industry-standard projects.v
₹ Call for Attractive Discounts
Admission Closes: 20th May 2023
No Cost EMI option 100% Money Back Guarantee Group Discounts (3 or more people together)
Speak to our Learning Advisor for details.
Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months EMI without paying any additional cost on interest.
Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
The Placement Desk has emerged as a favored destination for many organizations who come back year after year to recruit fresh talent nurtured at ChipEdge.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.
Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.
Best Trainers from industry with strong technical experience and currently working on latest technologies.
Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.
Learn on the go with Chipedge’s learning app. Access materials, attend live sessions anytime and anywhere.
Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24×7 availability.
ASIC Design Flow
Introduction to Verification
Verification Flow
Testbench Architecture
Verification Plan
Verilog is pre-requisite for this course. However essential Verilog concepts needed for verification will be refreshed.
ASIC Verification Flow, Verilog Vs SystemVerilog, Testbench Architecture, Migrating from Verilog to System Verilog.
Operations with 4-state Logic, Arrays, Structures, Unions, packed, unpacked, tagged.
Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.
Fork-join and its controls, Semaphore, Mailbox.
Need for OOPs in testbench, OOPs Terminology, Principles of OOPs, Inheritance, Polymorphysim, Copy (Shallow/Deep copy), Specilized classes, parameterized classes.
Dynamic Arrays, Associative Arrays, Array methods and usage, Tips for scoreboard Development
Need for Randomization, Controlling randomization, Constraints, Inline Constraints, Controlling constraints.
Need of Methodology, Constrained Random Verification, Verification Concepts
UVM Class Library, UVM Testbench, UVM Test, UVM Environment, UVM Scoreboard, UVM Agent, UVM Sequencer, UVM Sequence, UVM Driver, UVM Monitor
UVM Class Hierarchy, UVM Factory, UVM Config-db, UVM Callbacks, Parameterizing, Transactions, Phases, Event-pool, Field-macros, Messaging, Components vs Object
Basic TLM Communications, Communication Between Processes, UVM Analysis Communication
Data Item for Generation, Transaction Modelling, Driver Implementation, Sequencer, Monitor, Agent, Scoreboard, Environment, Test case, Top module
APB/AHB Slave IP Verification
Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.
Timings:
9:30 am to 1 pm, Saturday & Sundays
These timings are in IST (Indian Standard Timing) time zone.
Session Details:
9.30 am to 11.00 am – Lecture session
11.00 am to 11.30 am – Tea Break
11.30 am to 01.00 pm – Lab Session
The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.
Chipedge trainers are typically having 10 to 20 years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.
They are available on weekends only, during class hours for live interaction.
Instructor-led online courses on weekends are primarily designed for working professionals who want to upskill themselves.
With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.
Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.
Considering time constraints for all working professionals, you can attend these courses from home.
We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.
Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry world wide, not just in India.
Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.
It varies as per the course duration (short/long). please check the “Lab” tab, in course pages. Our course counselors can help you as well.
We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs. please check with our Course Counsellors.
Course completion certificates will be provided, whoever meets the course completion criteria.
Chipedge provides placement help to all candidates by providing them industry interview opportunities.