VLSI Design cycle involves preparing the design for fabrication at a selected foundry (TSMC, Global foundries.), with a specific technology node (10nm, 7nm.)
Design For Testability is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. With the increase in size & complexity of chips.
This Design verification course is designed and is delivered by practicing experts in Verification, as per the industry requirements.
Become proficient in Formal Verification and apply formal methods to ensure functional correctness of digital circuits and systems.
Training Needs Analysis: TNA
Designing the Right Customized Curriculum: RCC
Experiential training delivery: ETD
Measuring training effectiveness: MTE
Reskilling Brushup sessions: RBS
Tailored full time corporate training programs as per the requirment
Scheduled Live Online Training Programs.
Lab Usage Models (online) with Synopsys Tools.
Self-Learning Courses with Labs using Synopsys Tools.
RTL Design (Weekend/ Online)
Start Date: 4th May 2024
Formal Verification (Weekend/ Online)
Start Date: 20th April 2024
Design for Test (Weekend/ Online)
Start Date: 21st April 2024
Design Verification (Weekend/ Online)
Start Date: 6th April 2024