Certificate Course in
Physical Design (Online)

Learn Physical Design Course from Experts with 10+ yrs. of Industry Experience.
The course is taught using Synopsys Tools, IC Compiler 2, Prime Time, StarRC, IC Validator, with Online VLSI Lab Access.

Start Date

Batch 1: 23rd March 2024
Batch 2: 16th June 2024


5 Months

Training Type

Live Online Classes


VLSI Physical Design course, specially designed for working professionals to get comprehensive training to boost their career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements and is covered by trainers experienced in Physical Design.  

The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital design using Verilog. 

The course comprehensively covers Synthesis, Logical Equivalence Check (LEC),  Physical design flow including Floorplan, Powerplan, Placement, Clock Tree Synthesis & Routing, Static Timing Analysis, Physical Verification  and VLSI Physical Design Automation. 

Four projects will be covered during the course using 14nm/28nm library. Labs are on Industry standard tools from Synopsys like ICC2, Formality, starRC, Prime Time and IC Validator.

Course Fees

₹ Call for Attractive Discounts

No Cost EMI
100% Money Back Guarantee
Group Discounts

Course Delivery Model

Duration & Timing:

VLSI Tools & Lab

Synopsis Tools

Technology Libraries To be Used:

Lab Access:

Who Can attend this course


Placement Assistance

Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Why Choose ChipEdge

Online VLSI Lab

Synopsys Tools

Expert Trainers

Placement Assistance

Learning App

Industry Relevant Courses


MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design online course flow.

  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining Design for timing, area & power
  • Understanding Timing Library (.lib) format.
  • Synthesize Design
  • Timing Checks
  • The report, Analyze and debug results
  • Optimization Techniques
  • Saving the results

List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, Understanding the contents of each input file, qualifying the received inputs and sanity checks.

Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.

Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.

Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.

Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.

Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.

What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.

Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.

Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions,  loops, arrays, strings, file I/O and procedures.

Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.

2-3 projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.

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Demo Videos

Videos Reviews

What Our Learners Have to Say

I joined Chip Edge Technologies for learning Physical Design course. I understood the concepts very well and the Trainer explained nicely with examples. Lab gave me an overall view of the tool from Synthesis to P & R , Signoff tool like Primetime are explained well and how to debug if there are errors. Overall, My experience in ChipEdge was very good and knowledgeable.
Thumati Moses
I have accomplished Physical Design course from, I feel so lucky that I had chosen the weekend batch because there I was under the supervision of the most highly experienced trainers who had the great understanding of the industry. During pandemic ChipEdge shifted their placement work to Superset, which helped me to get more opportunities. If anyone looking to knowledge and opportunities in VLSI field I highly recommend ChipEdge from my personal experience.
Mohd shadmaan
I Choose a weekend physical design course from Chipedge, it is a good resource where you will never get any institute like ChipEdge. Nice faculty, they'll teach theory and lab parallelly. Lab's VPN is provided which can be used anytime. Once after I finished my course they started giving placement opportunities. I was placed through ChipEdge. I had a very good experience in my learning. Thank you so much ChipEdge.
Venkat Ramakrishna


Training is delivered in Instructor Led Virtual Classroom mode, on weekends. To attend the live sessions, you need to login into the chipedge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through VPN.

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge  trainers are typically having 10 to 20  years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs.  please check with our Course Counsellors.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

After a successful course completion, certificates will be provided.

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ChipEdge Admission Test (CVAT) 2024

For Job Oriented VLSI Certification Courses

Merit Scholarship Up to 80%

Pay After Placement Model

List of Courses

Design Verification (DV)
Physical Design (PD)

Course Start & CVAT Dates

Batch 1 – 24th June 2024

Batch 2 – 8th July 2024

Test Date :  Every Sunday Till 30th June