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ChipEdge now offers Integrated Internship courses for Students / Freshers (Enquire now).
Learn Physical Design Course from Professionals with 10+ yrs of Industry Experience. The course is taught using Synopsys Tools, IC Compiler 2, Prime Time, StarRC, IC Validator, with Online VLSI Lab Access.
29th April 2023
4 Months
Live Online Classess
VLSI Physical Design course, specially designed for working professionals to get comprehensive training to boost their career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements and is covered by trainers experienced in Physical Design.
The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital design using Verilog.
The course comprehensively covers Synthesis, Logical Equivalence Check (LEC), Physical design flow including Floorplan, Powerplan, Placement, Clock Tree Synthesis & Routing, Static Timing Analysis, Physical Verification and VLSI Physical Design Automation.
Four projects will be covered during the course using 14nm/28nm library. Labs are on Industry standard tools from Synopsys like ICC2, Formality, starRC, Prime Time and IC Validator.
₹ CALL FOR ATTRACTIVE DISCOUNTS
Admission Closes: 22nd April 2023
No Cost EMI
100% Money Back Guarantee
Group Discounts
Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months EMI without paying any additional cost on interest.
Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
The Placement Desk has emerged as a favored destination for many organizations who come back year after year to recruit fresh talent nurtured at ChipEdge.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.
Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.
Best Trainers from industry with strong technical experience and currently working on latest technologies.
Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.
Learn on the go with Chipedge’s learning app. Access materials, attend live sessions anytime and anywhere.
Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24×7 availability.
MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design online course flow.
List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, Understanding the contents of each input file, qualifying the received inputs and sanity checks.
Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.
Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.
Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.
Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.
Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.
Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.
What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.
Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.
Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.
Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.
2-3 projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.
Training is delivered in Instructor Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login into the chipedge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through VPN.
Timings:
9:30 am to 1 pm, Saturday & Sundays
These timings are in IST (Indian Standard Timing) time zone.
Session Details:
9.30 am to 11.00 am – Lecture session
11.00 am to 11.30 am – Tea Break
11.30 am to 01.00 pm – Lab Session
The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.
Chipedge trainers are typically having 10 to 20 years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.
They are available on weekends only, during class hours for live interaction.
Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.
With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.
Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.
Considering time constraints for all working professionals, you can attend these courses from home.
We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.
Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.
Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.
It varies as per the course duration (short / long). please check “Lab” tab, in course pages. Our course counselors can help you as well.
We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs. please check with our Course Counsellors.
We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs. please check with our Course Counsellors.
Chipedge provides placement help to all candidates by providing them industry interview opportunities.
Course completion certificates will be provided, whoever meets the course completion criteria.