Physical Design Course for Students/Freshers (UG/PG)

Kick Start your VLSI Career by Joining this Placement Assisted Course, Designed as Per Industry Skill Requirements and Delivered by Industry Experts. Using Synopsys Tools Design Compiler, ICC2, Prime Time, IC Validator, StarRC.

expert trainers

Synopsys Tools

100% Money Back Guarantee

expert trainers

Online VLSI Lab Access

Placement Assistance

Placement Assistance

Start Date

16th January 2023


5 Months

Training Type

Live Online Classess


VLSI Physical Design course, specially designed for fresh graduates to get comprehensive training to start a career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements and is covered by trainers experienced in Physical Design.  

The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital design using Verilog. 

The course comprehensively covers Synthesis, Logical Equivalence Check (LEC),  Physical design flow including Floorplan, Powerplan, Placement, Clock Tree Synthesis & Routing, Static Timing Analysis, Physical Verification  and VLSI Physical Design Automation. 

Four projects will be covered during the course using 14nm/28nm library. Labs are on Industry standard tools from Synopsys like ICC2, Formality, starRC, Prime Time and IC Validator.

Course Fees

₹ Call for Attractive Discounts

No Cost EMI option
100% Money Back Guarantee
Merit Based Discount Upto 30%
Group Discounts (3 or more people together)

Speak to our Learning Advisor for details.

At the end of the course the candidate will be able to :

  • Understand the input files including timing and physical standard cell library,  technology files and TLU+ files. 
  • Perform Synthesis by setting the timing constraints to obtain gate level netlist file and Synopsys design constraint file for a given RTL code
  • To import all the input files and create a database to run Physical Design flow
  • Perform Floorplan, Powerplan, Placement, CTS and Routing.
  • Perform Static Timing analysis and fix various violations
  • Perform Physical verification including Design Rule Checks (DRC) and Layout v/s Schematic (LVS) and fix the violations.

Course Delivery Model

Duration & Timing:

VLSI Tools & Lab

Synopsys Tools:

Technology Libraries To be Used:

Lab Access:

Who Can attend this course


Placement Assistance

Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.

The Placement Desk has emerged as a favored destination for many organizations who come back year after year to recruit fresh talent nurtured at ChipEdge.

We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Admission Procedure

There are 3 Simple process in the Admission Process which are detailed below:

Step 1: Online Eligibility Test

Take online test for 60 mins with 40 MCQs. Syllabus includes Aptitude, Digital Electronics, Electronic Devices ..etc

Step 2: Interview

This process includes further assessment of your fundamentals knowledge and soft skills. It will be conducted over a video call.

Step 3: Seat Confirmation

Enroll in the course, if selected. Start your preparation by getting access to the pre-requisite materials.

Why Choose ChipEdge ?

Industry Relevant Courses
Comprehensive list of VLSI courses, from Design to Tape-out in both Analog and Digital domains.
Synopsys Tools

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Expert Trainers

Best Trainers from industry with strong technical experience and currently working on latest technologies.

Placement Assistance

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning App

Learn on the go with Chipedge’s learning app. Access materials, attend live sessions anytime and anywhere.

Online VLSI Lab

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24×7 availability.


  • Introduction to Linux
  • Command Line Operators
  • File Operations
  • Processes
  • Text Editors
  • Text Manipulating
  • Network Operations
  • Special Keystrokes
  • Assessment and Quizzes

  • Number System, Boolean Algebra, SOP and POS, K-Map
  • Combinational circuits
  • Sequential circuits
  • Finite State machines
  • Frequency Division
  • Setup and Hold time checks
  • Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations
  • FIFO Depth Calculation
  • Assessment and Quizzes

  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode - Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, DIffusion, Ion Implementation, Lithography
  • Assessment and Quizzes

  • Introduction to Verilog
  • Applications of Verilog HDL
  • Verilog HDL language concepts
  • Verilog language basics and constructs
  • Data Types, Nets and registers, Arrays
  • Verilog Operators : Logical operators, Bitwise and Reduction operators, Concatenation and conditional operators, Relational and arithmetic, Shift and Equality operators, Operators precedence.
  • Type of assignments : Continuous assignments, Inter/Intra assignments, Blocking and Non-Blocking assignments, Execution branching, Tasks and Functions
  • Finite State Machine (FSM) : Basic FSM structure, Moore Vs Mealy, Common FSM coding styles, Registered outputs
  • Assessment and Quizzes

  • ASIC Design flow and role of Synthesis
  • Synthesis flow
  • writing timing constraints in SDC format
  • constraining the design for timing 
  • power, area goals, set optimization techniques
  • synthesize the design
  • generate and analyze the reports, save the netlist and SDC

  • Formal Verification
  • Understanding & Matching compare points
  • Debugging non equivalent points
  • What-If Analysis

Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions,  loops, arrays, strings, file I/O and procedures.

Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.

Introduction to physical designand Physical Design Flow, Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file, Sanity checks.

Goals of Floorplanning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines,  channel-width estimation.

Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power consumption. Why Low power and low power techniques. Electro-migration analysis.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.

STA Overview and concepts, Basic timing checks (setup, hold), understanding timing constraints(SDC), timing corners, timing report analysis.

General optimization techniques, typical causes for timing violations and strategies for fixing the same, Pre-CTS optimization to Fix setup violations.

Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,

Post-CTS optimization: Fixing Setup and Hold violations.

Goals of Routing, Stages of Routing:  Global Routing, Track assignment and Detail Routing, Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.

Post layout STA using SPEF, Multi Mode Multi Corner STA, Derating factors, PVT, OCV Variations, Crosstalk Analysis.

What is ECO, Types of ECO, Timing & Functional ECO, Performing the ECO placement and routing.

Physical Verification (DRC, LVS), IR drop analysis, Electro-Migration Analysis.

Projects will be given converging Netlist to GDS II flow.  Various projects that will allow the students to understand the intricacies of implementation for the minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry.  Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.

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Demo Videos

Videos Reviews

Learner Reviews

I had completed my BE and I was looking for a career change. Since I had no idea about this field, whatever concepts I was learning here were new to me. Trainer support here was very good as he had a great patience and was always ready to explain concepts repeatedly till we got that.
Rakshith M A
I have done a Physical design course from ChipEdge. It is the best platform for anyone to start their career in the VLSI domain. The trainer's interact with each learner in a very friendly way. We also had industry level expert sessions every week which helped us to gain knowledge at industry level.
Bharath Yadav
I have joined a physical design course in 2020. I have to say teaching is good and lab access via VPN is 24*7 available. They provided a seamless experience all the way through coaching. Good experience with Chipedg.
Leela krishna Namburi


Considering the covid pandemic, we have converted the job oriented courses with regular class room training to Virtual Class /Live Online Training Model.

You will attend the instructor led online classes from home, including labs. 

Except changing the delivery model from offline to online, everything else remains the same ..which includes duration of the course, syllabus, faculty,  labs, projects, placements.

The Minimum Qualification Required Is An Educational Background In Electronics.  This Could Include

  • B. Tech/B.E In ECE / EEE / Telecom / Instrumentation.
  • M.Tech/M.Sc In VLSI / Embedded / Power Electronics / Digital Electronics / Digital Communications.

Year of Passing:

  • For freshers without job experience:  2020 / 2021
  • For Engineers with experience in some domain:  2019 or earlier.


one should have 60% or above percentage throughout the academics

Trainer for Physical Design is having 12+ yrs of experience with a mix of industry and academic. He is passionate to share the knowledge and has excellent teaching skills. 

We Provide Placement Assistance By Arranging Interview Opportunities With Hiring Companies. This is complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.

We extend placement assistance, till one gets job.  To Ensure Successful Placements, We Provide Added Support Including Mentorship, Fundamentals Classes, Soft Skills Training, Mock Interviews Etc.

We provide comprehensive placement assistance, but we do not give any placement guarantee.  We provide quality training and interview opportunities to all our learners;  but how you utilize the opportunities and crack the interviews will solely depend on you.

As per our knowledge, most of the training organizations/colleges, even premium colleges like IITs/NITs/IIMs, they do not guarantee the placement. As per the reputation of the organization, companies do visit for hiring and candidates gets jobs. It depends on the candidates, how they utilize the campus for learning and proving his/her talent, when opportunity is given. 

Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In-Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 12.5 Lakhs.

Each year many companies visit ChipEdge for recruiting the various positions because of the quality training that we offer.  Few of the Service Companies include Altran, HCL, L&T, Synapse, Insemi, Cerium, sankalp, Tessolve, ..etc.

Product Companies (MNCs) like Intel, Samsung, Synopsys, MediaTek, Global Foundries, Microsemi ...etc visit us regularly for hiring.

For a complete list of companies visit

Internship option available for students, integrated with the job-oriented course.

The Internship model has 2 phases.

Phase1 – Learning:  4 months

Learning respective domain knowledge in 4 months, along with hands-on labs with VLSI tools.

Phase2 – Application (Projects):  2 months

Application of your learning in projects. one project will be part of course work, which completes in 5 months.

Whoever chooses the internship option, the extra project will be provided for the 6th month along with lab access and guidance from the technical experts.  

For further details, please check with our Learning Advisor.

We use 14nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies dont have these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.


Providing real time projects is not feasible in a VLSI Training environment. The projects we provide are of similar complexity but of a medium size as executed in the industry. For Learning purposes these projects are good enough. Many working professionals & students achieved success, by working on these projects.

VLSI Companies send their engineers to chipedge, to get their engineers trained on these projects. 


We do have installment options for some courses. No Cost EMI option is available through our financial partner organizations, who provide loans for training programs.

please check with our Learning Advisors.

ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals. If you are not happy with the course quality, 100% of your fee will be refunded. 

Please visit the refund policy for more details.

Sorry, GST is mandatory for VLSI physical design course fee payments and tax invoices will be provided to you. We follow the Govt Tax Laws strictly, as part of our corporate governance policy.

We understand 18% GST is significant amount. We have recommended Govt of India, to consider reducing the GST for skill development programs. We are hopeful, they will reduce in future.