Accelerate Your VLSI Career and Gain Expertise with

Physical Design Certification Course

Start Date

10th June 2024(Batch 1)
08th July 2024 (Batch 2)


6 Months

Training Type

Offline Classes


VLSI Physical Design course, specially designed for fresh graduates to get comprehensive training to start a career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements and is covered by trainers experienced in Physical Design.

The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital design using Verilog.

The course comprehensively covers Synthesis, Logical Equivalence Check (LEC), Physical design flow including Floorplan, Powerplan, Placement, Clock Tree Synthesis & Routing, Static Timing Analysis, Physical Verification.

2 projects will be covered during the course using 14nm/28nm library. Labs are on Industry standard tools from Synopsys like ICC2, Formality, starRC, Prime Time and IC Validator.

Course Fees

No Cost EMI option

Merit scholarships – 80% of fee

Pay after placement Model

Speak to our Learning Advisor for details.

Course Highlights

Course Delivery Model

Duration & Timing

VLSI Tools & Lab

Synopsys Tools:

Technology Libraries To be Used:

Who Can attend this course


Placement Assistance

Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Pay After Placement

For Training and Certification

Pay only 60% of the Course fee 

After Placement

Pay the remaining 40% of the after getting placed successfully.

Admission Test Process

Batch 1: 10th June 2024 | Test Date: 19th May
Batch 2: 08th July 2024 | Test Date: 2nd June  

Admission Test Dates

 Starting 19th May on Every Sunday till 30th June

Step 1: Fill the Form

Step 2: Registration Payment
₹ 299

Step 3: Prepare for the Test

C-VAT 2024 Test Syllabus

Admission Procedure

Step 1: Online Admission Test

Take online test for 90 mins with 60 MCQs. Syllabus includes Aptitude, Digital Electronics, Electronic Devices.

Step 2: Interview

This process includes further assessment of your fundamentals knowledge and soft skills. It will be conducted over a video call.

Step 3: Seat Confirmation

Enroll in the course, if selected. Start your preparation by getting access to the pre-requisite materials.

Why Choose ChipEdge

Online VLSI Lab

Synopsys Tools

Expert Trainers

Placement Assistance

Learning App

Industry Relevant Courses


  • Introduction to Linux
  • Command Line Operators
  • File Operations
  • Processes
  • Text Editors
  • Text Manipulating
  • Network Operations
  • Special Keystrokes
  • Assessment and Quizzes
  • Number System, Boolean Algebra, SOP and POS, K-Map
  • Combinational circuits
  • Sequential circuits
  • Finite State machines
  • Frequency Division
  • Setup and Hold time checks
  • Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations
  • FIFO Depth Calculation
  • Assessment and Quizzes
  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode – Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, DIffusion, Ion Implementation, Lithography
  • Assessment and Quizzes
  • Introduction to Verilog
  • Applications of Verilog HDL
  • Verilog HDL language concepts
  • Verilog language basics and constructs
  • Data Types, Nets and registers, Arrays
  • Verilog Operators : Logical operators, Bitwise and Reduction operators, Concatenation and conditional operators, Relational and arithmetic, Shift and Equality operators, Operators precedence.
  • Type of assignments : Continuous assignments, Inter/Intra assignments, Blocking and Non-Blocking assignments, Execution branching, Tasks and Functions
  • Finite State Machine (FSM) : Basic FSM structure, Moore Vs Mealy, Common FSM coding styles, Registered outputs
  • Assessment and Quizzes
  • ASIC Design flow and role of Synthesis
  • Synthesis flow
  • writing timing constraints in SDC format
  • constraining the design for timing 
  • power, area goals, set optimization techniques
  • synthesize the design
  • generate and analyze the reports, save the netlist and SDC
  • Formal Verification
  • Understanding & Matching compare points
  • Debugging non equivalent points
  • What-If Analysis

Features of TCL and Applications. TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions,  loops, arrays, strings, file I/O and procedures.

Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.

Introduction to physical designand Physical Design Flow, Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file, Sanity checks.

Goals of Floorplanning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines,  channel-width estimation.

Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power consumption. Why Low power and low power techniques. Electro-migration analysis.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.

STA Overview and concepts, Basic timing checks (setup, hold), understanding timing constraints(SDC), timing corners, timing report analysis.

General optimization techniques, typical causes for timing violations and strategies for fixing the same, Pre-CTS optimization to Fix setup violations.

Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,

Post-CTS optimization: Fixing Setup and Hold violations.

Goals of Routing, Stages of Routing:  Global Routing, Track assignment and Detail Routing, Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.

Post layout STA using SPEF, Multi Mode Multi Corner STA, Derating factors, PVT, OCV Variations, Crosstalk Analysis.

What is ECO, Types of ECO, Timing & Functional ECO, Performing the ECO placement and routing.

Physical Verification (DRC, LVS), IR drop analysis, Electro-Migration Analysis.

Projects will be given converging Netlist to GDS II flow.  Various projects that will allow the students to understand the intricacies of implementation for the minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry.  Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.

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Videos Reviews

What Our Learners Have to Say

I had completed my BE and I was looking for a career change. Since I had no idea about this field, whatever concepts I was learning here were new to me. Trainer support here was very good as he had a great patience and was always ready to explain concepts repeatedly till we got that.
Rakshith M A
I have done a Physical design course from ChipEdge. It is the best platform for anyone to start their career in the VLSI domain. The trainer's interact with each learner in a very friendly way. We also had industry level expert sessions every week which helped us to gain knowledge at industry level.
Bharath Yadav
I have joined a physical design course in 2020. I have to say teaching is good and lab access via VPN is 24*7 available. They provided a seamless experience all the way through coaching. Good experience with Chipedge.
Leela krishna Namburi


Students pay 60% of the course fee upfront during admission. The remaining 40% is paid after securing a job, within 12 months of completing the course. If students find their own job, they get a 10% fee waiver.

Toppers in the National Level Aptitude Test qualify for up to an 80% scholarship. Eligibility includes a CGPA of at least 7, with preference for CGPA above 8, for B.Tech  and M.Tech graduates of 2023/2024.

We provide placement assistance by arranging interview opportunities with hiring companies. This is complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.

We provide placement support until candidate gets job. To Ensure Successful Placements, We provide added support including mentorship, fundamentals classes, soft skills training, mock interviews Etc.

Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 12.5 Lakhs.

Though 3-4 LPA appears similar to software salaries, your real growth comes after 3 years. First 2-3 years are to be considered as career building phase, to learn as much as you can and do not compare with others / IT salaries.   Your knowledge will be your power and your career / salary growth from 4th year onwards depends on your talent/knowledge.

Each year many companies visit ChipEdge for recruiting the various entry level positions because of the quality training that we offer. 

For complete list of companies visit

We use 28nm,14nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.

We do have installment options for some courses. EMI option is available through our partner organizations, who provide loans for training programs. Please check with our learning advisors.

Get Upto 40% OFF

ChipEdge Admission Test (CVAT) 2024

For Job Oriented VLSI Certification Courses

Merit Scholarship Up to 80%

Pay After Placement Model

List of Courses

Design Verification (DV)
Physical Design (PD)

Course Start & CVAT Dates

Batch 1 – 10th June 2024

            Test Date : 5th & 19th May

Batch 2 – 8th July 2024

            Test Date : 2nd June