The most sensitive component of a MOS transistor is the gate oxide. During the construction of an ASIC, special care must be taken to safeguard it from damage both throughout the fabrication process and during the functioning of the ASIC. Some unwanted impacts can arise throughout an actual manufacturing process. The antenna effect in VLSI, also known as plasma-induced gate-oxide damage or plasma-induced damage, is one of them.
In VLSI, the term “antenna effect” refers to the charge collecting effect, not to the antenna device. A large quantity of charge is often induced during plasma etching and other procedures. The antenna effect in VLSI is a phenomenon that can harm the gate oxide of MOS transistors during the fabrication process, particularly when using plasma etching. In this post, we will look into the antenna effect and the factors that contribute to it.
The antenna effect in VLSI is also known as plasma generated gate oxide damage. It is a phenomenon that can result in yield and reliability issues when MOS integrated circuits are manufactured.
What is The Reason Behind The Antenna Effect in VLSI?
If a conducting material or wire is linked to the device’s gate, the wire acts as an antenna, inducing a considerable amount of charge, and diodes produced by drain and source diffusion layers can conduct a significant amount of current. Finally, the antenna effect causes gate failure or I-V characteristics to deteriorate.
Changing threshold voltage; lower device life expectancy; increased gate leakage are some of the issues that might arise.
Antenna guidelines have been established in order to prevent the concerns mentioned above.
- One solution is to split the wire into two sections and link the wire and a gate to the buffer layer.
- Another option is to attach the diode to the wire and establish a discharge path during the etching process.
The word ‘Antenna Effect’ may not immediately conjure up images of electromagnetic radiation or transmitter-receiver systems, however this is not the case. As a result, it has another common name: “Plasma Induced Gate Oxide Damage,” which accurately describes the impact. This is a result induced by Gate Oxide Damage generated by the Plasma Etching process during the production of VLSI devices, as the name implies.
When and How Does It Occur?
Although the antenna effect in VLSI occurs during the chip fabrication process, particularly during plasma etching, the avoidance mechanism should be established from the physical design stage. During the physical signoff step, the fabrication laboratory produces the antenna rule file, which must be examined and cleaned according to the antenna rule.
The fabrication flow begins with the fabrication of the FEOL (Front End Of Line), which includes the manufacture of all MOS transistors. BEOL (Back End Of Line) manufacturing begins after the FEOL fabrication is completed, which comprises the manufacture of metal interconnects. During BEOL manufacture, the antenna effect enters the picture.
Plasma etching is used to produce metal interconnects in the IC manufacturing process. Plasma etching is a selective etching method that is dry and anisotropic. During the etching process of metals, plasma comprises high-energy ions and radicals, which are gathered by metal interconnects.
What is The Consequence of the Antenna Effect and Its Solutions?
Antenna Violation: Antenna Violation occurs when the antenna ratio exceeds a value specified in a Process Design Kit (PDK). The antenna ratio is the ratio of the gate area to the gate oxide area. The amount of charge collection is determined by the area/size of the conductor (gate area).
Antenna Violation Solutions:
Metal Jumpers: Break signal lines and use jumpers to route them to the top metal layers. The lengthy wire connecting the gate and route to the higher metal layer is broken when a jumper is inserted. As a result, it grows shorter and less capable of charging. If an antenna violation occurs on a metal layer, use upper metal layers as a metal jumper because all of the lower levels have previously been produced.
Diode Insertion: Connecting reverse biased diodes near the gate input when a net is violated gives a discharge channel to the substrate, saving the transistor’s gate. The addition of a diode increases the area as well as the capacitance, resulting in a delay increase.
Conclusion:
The circumstances that lead to development of antenna effect in VLSI, are defined empirically for each procedure and are dependent on the technology employed to create the chip. Once they’ve been determined, they can be used to create a set of antenna rules that can be programmed, similar to traditional DRC rules. Learn more about antenna effect in detail by registering for online VLSI courses on Chipedge which is the best VLSI training institute in India for online VLSI training. There are several online VLSI courses on this website for starting a successful career in VLSI industry. This VLSI training institute offers various VLSI job oriented courses like Physical Design course, Design Verification course, ASIC verification course, DFT course , chip design course and many more. Register yourself for the best courses today!
