RTL Design Course
Learn the in-demand skill in VLSI job market and accelerate your career growth. Study the RTL Design Course with Live Online Sessions delivered by senior industry professionals with 10 – 20 yrs of industry experience, using Synopsys tools.
100% Money Back Guarantee
Online VLSI Lab Access
Live Online Classess
RTL Design Online Course Overview
RTL Design Engineer’s scope of work has changed in the last few years. It has changed mostly into tool intensive job than pure coding. Most of the development of new chips is driven by integrating readily available Design IPs, than developing fresh RTL Codes.
RTL Design Engineer nature of work includes RTL Coding using Verilog/System Verilog, RTL integration which involves writing glue logic as needed for integrating the IPs, tool intensive works mainly on Linting, CDC (clock domain crossing) checks on a daily basis. Some roles include Synthesis, STA (Static Timing Analysis), LEC (logical equivalence checks) tasks as well.
RTL Design Course comprehensively covers micro architecture, digital design partitioning, RTL Development using synthesis friendly verilog coding styles. Followed by Linting using Spyglass tool, which exhaustively checks various rules and flags errors/warnings for fixing. CDC checks are done with SpyGlass for checking various CDC rules.
RTL Design in VLSI covers various rules along with examples and how to analyze, fix them. Each module of RTL Design Online Course has associated hands on labs and multiple projects, to give good exposure to industry complexity.
Synopsys SpyGlass tools is widely used in the industry as sign off tool for LINT, CDC checks.
At the end of the course, the candidate will be able to do
- Develop RTL for a given specification in a correct-by-construction approach.
- Understand any given RTL in verilog/System Verilog and write additional RTL as needed, like wrappers, glue logic.
- Will be able to run Lint, CDC tools and Analyze the violations. And work with RTL team to fix the same.
- Will be able to do logic synthesis, formal verification / LEC with DC, Formality.
- Will be able to generate and analyze the timing reports.
- WIll have basic knowledge of Low power techniques using UPF
Course Delivery Model
Duration & Timing:
VLSI Tools & Lab
Technology To be Used: 14nm Libraries
Who Can attend this course
No Cost EMI
Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months EMI without paying any additional cost on interest.
Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
The Placement Desk has emerged as a favored destination for many organizations who come back year after year to recruit fresh talent nurtured at ChipEdge.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.
Why Choose ChipEdge ?
Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.
Best Trainers from industry with strong technical experience and currently working on latest technologies.
Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.
Learn on the go with Chipedge’s learning app. Access materials, attend live sessions anytime and anywhere.
Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24×7 availability.
- Introduction to micro architecture definition
- Digital Design Partitioning
- RTL Design Development.
The Learner is trained to gain the ability to develop RTL for a given specification in a correct-by-construction approach.
- Introduction to Verilog & Modeling Styles with Examples
- Some examples (Encoder, comparator, etc) and their Verification
- sequential – DFF, Shift registers and their Verification
- Tasks and Functions
- Inter/Intra Assignment, Blocking and Non-Blocking Assignments
- Parameters and Parameterised modules
- Coding styles in FSMs
- RTL for synthesis
- RTL Coding guidelines
- Introduction to ASIC Design Flow
- Role of Front end design in ASIC Design Flow.
- Role of RTL Design in Front End Design Flow.
- Role of EDA Tools in Front End Design / ASIC Design flow.
- Purpose of RTL & Linting
- How does it work?
- Typical Lint Targets
- Lint Example
- SpyGlass Tool Flow
- SpyGlass Design Read
- Goal Selection & Setup
- Run Analysis & Debug
- SpyGlass Tool Setup
- CDC Basics
- Clock Domain & Clock Groups
- CDC Problems & Solutions
- CDC Synchronization Techniques
- Issues in CDC flow
- Constraints vs Waivers
- Capturing Design Intent in CDC Constraints
- SpyGlass Tool setup
- Run Analysis and Debug
- Abstract CDC flow
- Hierarchical waiver in CDC with SoC methodology
- Introduction to Synthesis
- Synthesis Flow
- Constraining the design for timing, area, power
- Creating timing constraints in SDC format
- Understanding & Exploring .lib libraries
- Synthesize Design
- Timing Analysis & Optimization
- Generate reports, Analyze and debug results
- STA overview & concepts
- Clocking – Handling clock muxes, clock dividers
- Generated clocks, Clocking Exceptions
- Timing Exceptions
- Generate & analyze timing reports
- Timing ECOs generation
- Loading reference & implemented design
- Understanding & Matching compare points
- Verifying design & interpreting results
- Debugging the Non Equivalents
Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.
9:30 am to 1 pm, Saturday & Sundays
These timings are in IST (Indian Standard Timing) time zone.
9.30 am to 11.00 am – Lecture session
11.00 am to 11.30 am – Tea Break
11.30 am to 01.00 pm – Lab Session
The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.
Chipedge trainers are typically having 10 to 20 years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.
They are available on weekends only, during class hours for live interaction.
Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.
With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.
Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.
Considering time constraints for all working professionals, you can attend these courses from home.
We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.
Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry worldwide, not just in India.
Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.
It varies as per the course duration (short/long). please check the “Lab” tab, in course pages. Our course counselors can help you as well.
We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs. please check with our Course Counsellors.
Course completion certificates will be provided, whoever meets the course completion criteria.
Chipedge provides placement help to interested candidates, who need to register with placement desk. Its complimentary service without any fee / cost.