Advanced Peripheral Bus (APB) is a protocol of the Advanced Microcontroller Bus Architecture (AMBA) family. The most recent version of APB is v2.0, which was released as part of the AMBA 4 release. It is a low-cost interface that has been tuned for low power consumption and low interface complexity. It is a Non-Pipelined protocol, unlike AHB, and is used to link low-bandwidth peripherals. It is typically used to link external peripherals to the SOC. Every transfer in APB requires at least two clock cycles to complete (SETUP Cycle and ACCESS Cycle). It can also communicate with AHB and AXI protocols through bridges.
Components of Advanced Peripheral Bus
The high-performance ARM processor is the Core of the system. Other components such as High-bandwidth on-chip RAM, DMA bus master, and High-bandwidth Memory Interface are linked to the Core via the System bus, which in this case is AHB. Other low bandwidth peripherals such as UART, Timer, Keypad, and PIO are connected to the System bus via the Bridge via the Peripheral bus, which in this case is the Advanced Peripheral Bus. In this situation, the Bridge serves as the AHB Slave for the Core Master. It also serves as the APB Master for the other low-bandwidth external peripherals. In most cases, no component will be responsible for APB transfers. The AHB to APB Bridge is the single component in a system that serves as the APB master.
Advanced Peripheral Bus is a simple bus that is easy to work with, due to its:
- Low-cost
- Low-power
- Low-complexity
- Low-bandwidth
- Non-pipelined
- Ideal for peripherals
Error Response
When there is a mistake in the transfer, Slave signals the error response by asserting the PSLVERR signal. When PSEL, PENABLE, and PREADY are all HIGH, PSLVERR is considered genuine. It is advised, but not required, to keep PSLVERR low while it is not being sampled. Transactions receiving an incorrect answer may or may not have modified the status of the peripheral.
Conclusion
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