Begin Your VLSI Career with the Most
In-Demand Skill

Design Verification Certification Course

Start Date

10th June 2024 (Batch 1)
08th July 2024 (Batch 2)

Duration

6 Months

Training Type

Offline Classes

Overview of Design Verification Course

ASIC Design Verification (DV), is also called RTL/ Functional Verification, which involves verification of the RTL design for its functionality. As the RTL design has to be exhaustively verified for its functionality, the demand for a DV Engineers in the VLSI Industry is comparatively more than other skill sets.
Design Verification in VLSI course comprehensively covers digital design, Verilog for verification, System Verilog and UVM with multiple examples, labs and projects. A couple of Industry standard protocols will be covered during the Design Verification in VLSI course which will give an implementation experience for projects.
VLSI Design & Verification course is designed by keeping the latest industry requirements in mind and delivered by practicing experts in Design Verification. Importance is given to cover all the relevant concepts, latest methodologies, with a good emphasis on hands-on labs and 2 projects, to give good exposure to industry complexity.

Course Fees

No Cost EMI option

Merit scholarships – 80% of fee

Pay after placement Model

Speak to our Learning Advisor for details.

Program Highlights

Course Delivery Model

Duration & Timing

VLSI Tools & Lab

Tools to be used:

Who Can Attend this Course

Payments

Placement Assistance

Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Pay After Placement

For Training and Ceritification

Pay only 60% of the Course fee 

After Placement

Pay the remaining 40% of the after getting placed successfully.

Admission Test Process

Batch 1: 10th June 2024
Batch 2: 08th July 2024

Admission Test Dates

 Starting 19th May on Every Sunday till 30th June

Step 1: Fill the Form

Step 2: Registration Payment
₹ 299

Step 3: Prepare for the Test

C-VAT 2024 Test Syllabus

Admission Test Process

Admission Procedure

Step 1: Online Admission Test

Take online test for 90 mins with 60 MCQs. Syllabus includes Aptitude, Digital Electronics, Electronic Devices .

Step 2: Interview

This process includes further assessment of your fundamentals knowledge and soft skills. It will be conducted over a video call.

Step 3: Seat Confirmation

Enroll in the course, if selected. Start your preparation by getting access to the pre-requisite materials.

Why Choose ChipEdge

Online VLSI Lab

Synopsys Tools

Expert Trainers

Placement Assistance

Learning App

Industry Relevant Courses

Design Verification Course Curriculum

• Introduction to Linux, 
• Command Line Operators,
• File Operations, Processes,
• Text Editors,
• Text Manipulating,
• Network Operations,
• Special Keystrokes
• GVIM

• Number System, Boolean Algebra,
• SOP and POS, K-Map,
• Combinational circuits, Sequential
circuits,
• Finite State machines,
• Frequency Division,
• Setup and Hold time checks,
• Advance Design Issues: Metastability,
Noise Margins, Power, Fanout, Timing
Considerations,

Verilog HDL

• ASIC Flow, Module, declaration and Instantiation, Components of
simulation, Procedural blocks, Lexical convections.
• Data types, Module Parameters, Operators, Primitives, Functional.
representation in Verilog.
• Arrays, Memories, System tasks, compiler Directives, Continuous and
Procedural Assignments, Examples of Blocking and Non-blocking statement.
• Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.
• Task, Functions, Difference between task and Function.

Verification Lab

Combinational circuits
• 2×1 Multiplexer, 4×1 Multiplexer
• 4:2 Decoder
• Half Adder and Full Adder
• Priority encoder
• Sequential circuits
• D-ff
• SISO
• Counters
• Design and Verification of RAM.
• Design and Verification of FSM (1 FSM to be done by the students for final assessment)

SV Testbench Architecture, Verilog vs System Verilog, SV Data types: 2 state vs 4 state variables, Dynamic Arrays, Associative Arrays, and its Usage.

Strings, Unions, Structures, Enumerated data Types, Events.

SV Interfaces: Interface ports, Mod ports, Clocking blocks, Virtual Interface, Program blocks.

SV Class, Inheritance, this operator, super operator, shallow copy, deep copy, parameterized classes, typedef classes, polymorphism, abstract class, encapsulation, dynamic casting, scope resolution operators.

IPC: Event, Mailbox, Semaphores Randomization & Constraints: Basics, specifying constraints, methods in constraints, random stability, random sequences, and random case.

Introduction, Advantage and types of assertions, Sequence & property, writing assertion using operators & system tasks.

Code coverage, functional coverage, cover groups, cover points, cover bins, cross coverage, coverage options & methods.

Limitations of SV testbench, Migrating from SV to UVM, UVM Architecture, UVM Class Hierarchy.

UVM Phase categorization, UVM Reporting.

TLM 1.0, TLM 2.0, Examples.

UVM Field Macros, Factory registration, create method, factory override.

UVM config database, construction of UVC, sequence generation, Sequences, Virtual Sequencer, Virtual Sequences.

1. Verification of APB slave
2. Verification of AHB protocol

Enquire Now

Videos Reviews

Learner Reviews

I have attended a VLSI Design Verification course. Initially I was not much aware of the VLSI domain. ChipEdge provided me a great platform for learning VLSI. They provided VCS Synopsys tool access 24*7 through VPN. Trainers are really awesome. During this pandemic time, they also provide good placement opportunities.
Rabi Ahir
I have done a Design Verification course in Chipede. Training was excellent with good interaction. Recording facility is excellent for revision. Course was practically informative. The way of explaining is good. The course helped me to build confidence, valuable experience and learning.
Hemanth Kumar
I have completed Design Verification from ChipEdge. I got to know about this institute through my friends. Chipedge is the Best platform to start our career in the vlsi domain. Good placement opportunities are provided. They provide excellent training and trainers are well experienced and friendly.
Maneesha Murali

FAQs

Students pay 60% of the course fee upfront during admission. The remaining 40% is paid after securing a job, within 12 months of completing the course. If students find their own job, they get a 10% fee waiver.

Toppers in the National Level Aptitude Test qualify for up to an 80% scholarship. Eligibility includes a CGPA of at least 7, with preference for CGPA above 8, for B.Tech  and M.Tech graduates of 2023/2024.

We provide placement assistance by arranging interview opportunities with hiring companies. This is complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.

We provide placement support until candidate gets job. To Ensure Successful Placements, We provide added support including mentorship, fundamentals classes, soft skills training, mock interviews Etc.

Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 12.5 Lakhs.

Though 3-4 LPA appears similar to software salaries, your real growth comes after 3 years. First 2-3 years are to be considered as career building phase, to learn as much as you can and do not compare with others / IT salaries.   Your knowledge will be your power and your career / salary growth from 4th year onwards depends on your talent/knowledge.

Each year many companies visit ChipEdge for recruiting the various entry level positions because of the quality training that we offer. 

For complete list of companies visit https://chipedge.com/view-hiring-companies/

We use 28nm,14nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.

We do have installment options for some courses. EMI option is available through our partner organizations, who provide loans for training programs. Please check with our learning advisors.

Get Upto 40% OFF

ChipEdge Admission Test (CVAT) 2024

For Job Oriented VLSI Certification Courses

Merit Scholarship Up to 80%

Pay After Placement Model

List of Courses

Design Verification (DV)
Physical Design (PD)

Course Start & CVAT Dates

Batch 1 – 10th June 2024

            Test Date : 5th & 19th May

Batch 2 – 8th July 2024

            Test Date : 2nd June