Design Verification Certification Course

• Introduction to Linux, 
• Command Line Operators,
• File Operations, Processes,
• Text Editors,
• Text Manipulating,
• Network Operations,
• Special Keystrokes
• GVIM

• Number System, Boolean Algebra,
• SOP and POS, K-Map,
• Combinational circuits, Sequential
circuits,
• Finite State machines,
• Frequency Division,
• Setup and Hold time checks,
• Advance Design Issues: Metastability,
Noise Margins, Power, Fanout, Timing
Considerations,

Verilog HDL

• ASIC Flow, Module, declaration and Instantiation, Components of
simulation, Procedural blocks, Lexical convections.
• Data types, Module Parameters, Operators, Primitives, Functional.
representation in Verilog.
• Arrays, Memories, System tasks, compiler Directives, Continuous and
Procedural Assignments, Examples of Blocking and Non-blocking statement.
• Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.
• Task, Functions, Difference between task and Function.

Verification Lab

Combinational circuits
• 2×1 Multiplexer, 4×1 Multiplexer
• 4:2 Decoder
• Half Adder and Full Adder
• Priority encoder
• Sequential circuits
• D-ff
• SISO
• Counters
• Design and Verification of RAM.
• Design and Verification of FSM (1 FSM to be done by the students for final assessment)

Strings, Unions, Structures, Enumerated data Types, Events.

SV Interfaces: Interface ports, Mod ports, Clocking blocks, Virtual Interface, Program blocks.

IPC: Event, Mailbox, Semaphores Randomization & Constraints: Basics, specifying constraints, methods in constraints, random stability, random sequences, and random case.

Introduction, Advantage and types of assertions, Sequence & property, writing assertion using operators & system tasks.

Code coverage, functional coverage, cover groups, cover points, cover bins, cross coverage, coverage options & methods.

Limitations of SV testbench, Migrating from SV to UVM, UVM Architecture, UVM Class Hierarchy.

UVM Phase categorization, UVM Reporting.

TLM 1.0, TLM 2.0, Examples.

UVM Field Macros, Factory registration, create method, factory override.

UVM config database, construction of UVC, sequence generation, Sequences, Virtual Sequencer, Virtual Sequences.

1. Verification of APB slave
2. Verification of AHB protocol