Live VLSI Webinar Sessions and Webinar Recordings

Every month,
Free Expert Webinars

On Demand Webinars

Memory Architecture and SRAM cell design

Understanding basic SRAM architecture , SRAM cell functionality and design constraints

Date: June 29th, 2024
Time: 11:00 Am IST

Guest Speaker : Nutan Agarwal, Experienced in Physical IP design and Silicon Validation, particularly SRAM/ROM design, with a professional background at STMicroelectronics, Synopsys, and Arm.

AI / ML in Chip Design and Verification

Discover the keys to achieving success on AI/ML in Chip Design and Verification
in the VLSI industry through our upcoming webinar conducted by industry expert, Paul Kaunds

Gain in-depth knowledge on Impact, Use cases, Industry trends in using AI/ML to make Chip Design/Verification more efficient and robust.

Date: May 18th, 2024
Time: 10:00 Am IST

Speaker: Paul Kaunds , Strategic Advisor to Prodapt and Co-Founder of AI/ML/Quantum/Chip Product R&D, London-UK

Evolution of FPGA Technologies

Join us for an engaging webinar providing an introduction to Field-Programmable Gate Arrays (FPGAs), where we delve into their applications, evolution, and future prospects. Discover the career opportunities available in the exciting field of FPGAs and learn how to pave your path towards a rewarding career.

Date: April 20th, 2024
Time: 10:00 Am IST

Speaker: Paresh K Joshi , Principal Architect

The Role of DFT Engineer in SOC Design & Career Opportunities

The webinar covers VLSI Design Cycle, scope of Physical Design (PD), and the role of PD engineers within an organization.
How to build the skills required to become a Physical Design Engineer and career growth opportunities in this industry.

Date: March 16th, 2024
Time: 10:00 Am IST

Speaker: Mittu George P, DFT Engineer, Celton Semiconductors Pvt Ltd

The Significance of Quality Timing Constraints for ASIC Designs.

They say you are what you eat. The same analogy for VLSI design is quality of the design is quality of the constraints. Timing constraints play a very important role because it sets the tone for every stage of the design flow. When somebody refers to design complexity it is not just design size but also constraints the designer is dealing with. Reviewing constraints and making sure it meets design intent is very important. Better timing constraints lead to better timing closure .

During the session we will cover key timing constraints , impact of these constraints on the design flow, how to fix the constraints issue and also how it helps timing closure.

Date: February 17th, 2024

Speaker: Pradeep CR Director, Ausdia India Pvt Ltd

The Role Of Physical Design Engineer In VLSI Designs

The webinar delves into the VLSI Design Cycle, explores the realm of Physical Design (PD), and examines the crucial role PD engineers play within organizations. It also offers insights on developing the necessary skills to embark on a career as a Physical Design Engineer, along with potential pathways for career advancement within the industry.

Date: 20th January 2023

Time: 10 AM Onwards

Speaker: Dr. Abhinav, Physical Design Engineer, Celton Semiconductors Pvt Ltd

The Scope and Career Opportunities for Design Verification in Semiconductor (VLSI) Industry

This all-encompassing webinar aims to furnish foundational knowledge about the semiconductor industry, navigates you through the steps involved in crafting a System on Chip, gain insights into the integral role of verification engineer in ensuring the correctness and functionality of design components, the necessity for robust verification practices, various techniques, industry opportunities, and identify the essential skills required/ needed for a successful career as a verification engineer.

Date: 20th January 2023

Time: 10 AM Onwards

Speaker: Bhanu Macharla – Sr. Design verification Engineer, ChipEdge Technologies Pvt. Ltd.

Physical Design - Part 1: Synthesis Process | Synopsys Design Compiler Tool | Demo (Webinar 2)

This demo includes the information of tool usage and Physical Design Flow with respect to the Synthesis process.

Date : 6th January 2023