e-Internship Program

Q: Advanced Digital Design (1st Month)

Topics Covered : Advanced logic design, FSM, counters, and timing analysis. Learning Mode : Self-paced study with scheduled doubt-clearing sessions. Suggested Weekly Schedule : 4 hours of study + Periodic Sessions by Industry Professionals to Clear Doubts and Latest Trends Goal : Build a strong foundation to prepare for Verilog HDL.

Q: Verilog HDL & Verification (2nd Month)

Weeks 1-2 : Introduction to Verilog, coding, control structures, and simple modules Weeks 3-4 : Verification techniques, testbenches, and debugging. Learning Mode : Self-paced study, scheduled doubt-clearing sessions, and weekly lab assignments. Goal : Master Verilog coding and the verification of digital modules.

Q: Verification using Verilog (3rd Month)

Weeks 1-2 : Introduction to verification concepts and writing testbenches. Weeks 3-4 : Functional coverage, simulation techniques, assertions, and constraints. Learning Mode : Self-paced study, scheduled doubt-clearing sessions, and weekly lab assignments. Goal : Ensure the digital design behaves correctly and meets functional and timing requirements.

Q: Capstone Project – UART Verification (4th Month)

Project : Verification of a UART module, final report, and presentation. Learning Mode : Project work (self-paced with weekly milestones) and scheduled doubt-clearing sessions. Goal : Apply digital design and verification skills in a real-world project scenario.

Empowering the Next Generation of VLSI Engineers!

Start Date

18th January 2025

Duration

4 Months

Internship Mode

Online

About the Program

Our Flexible e-Internship in VLSI Design and Verification is an industry-oriented, 4-month online program tailored for 4th-year B.Tech ECE students. This program provides a perfect blend of self-paced learning, scheduled doubt-clearing sessions, and hands-on project work, giving students the flexibility they need while equipping them with real-world skills.

Duration: 4 Months (Flexible completion within 120 days)
Format: Self-paced Internship, Learn at your own pace within the 4-month duration

Program Fees

~~₹15,000~~ ₹10,000
Only for 1st 25 Students

*taxes applicable

Affordable pricing for students, with group discounts available.

Who Should Join?

Tools and Resources

Why Choose Our e-Internship Program?

Comprehensive Curriculum

Gain in-depth knowledge of advanced digital design, Verilog HDL, and design verification with a structured learning path.

Hands-On Project

Gain in-depth knowledge of advanced digital design, Verilog HDL, and design verification with a structured learning path.

Flexible Learning

Learn at your own pace within the 4-month duration. Weekly doubt-clearing sessions ensure you’re never stuck, even with a flexible schedule.

Industry-Relevant Skills

Learn with industry-standard tools like ModelSim and QuestaSim while gaining skills directly applicable to VLSI design roles.

Student Benefits

Real-World Experience

Industry-Aligned Skills

Mentorship and Guidance

Flexible Learning Schedule

Learning App

Certification & Project Portfolio

Program Curriculum & Structure

Advanced Digital Design (1st Month)

Topics Covered: Advanced logic design, FSM, counters, and timing analysis.
Learning Mode: Self-paced study with scheduled doubt-clearing sessions.
Suggested Weekly Schedule: 4 hours of study + Periodic Sessions by Industry Professionals to Clear Doubts and Latest Trends
Goal: Build a strong foundation to prepare for Verilog HDL.

Verilog HDL & Verification (2nd Month)

Weeks 1-2: Introduction to Verilog, coding, control structures, and simple modules
Weeks 3-4: Verification techniques, testbenches, and debugging.
Learning Mode: Self-paced study, scheduled doubt-clearing sessions, and weekly lab assignments.
Goal: Master Verilog coding and the verification of digital modules.

Verification using Verilog (3rd Month)

Weeks 1-2: Introduction to verification concepts and writing testbenches.
Weeks 3-4: Functional coverage, simulation techniques, assertions, and constraints.
Learning Mode: Self-paced study, scheduled doubt-clearing sessions, and weekly lab assignments.
Goal: Ensure the digital design behaves correctly and meets functional and timing requirements.

Capstone Project – UART Verification (4th Month)

Project: Verification of a UART module, final report, and presentation.
Learning Mode: Project work (self-paced with weekly milestones) and scheduled doubt-clearing sessions.
Goal: Apply digital design and verification skills in a real-world project scenario.

For Queries

Email: e-internship@chipedge.com
Phone: 080474 94767