The chip manufacturing process is complex and prone to flaws, which are referred to as faults. A fault is testable if a well-defined mechanism exists to disclose it in the real silicon. We need to incorporate more logic to make the task of identifying as many defects as possible in a design practicable. Design for testability (DFT) refers to design principles that make testing possible. Let us explore the most prevalent DFT approach for logic testing, known as Scan and ATPG in VLSI.
Also Read DFT Scan Types And Their Mechanism
ATPG and Scan
Scan refers to the internal change of a design’s circuitry to improve testability. ATPG in VLSI stands for Automatic Test Pattern Generation; this is the process of creating test patterns. In other words, Scan facilitates the pattern-generating process for detecting the previously described defects.
What are ATPG Tools?
The Automatic Test Pattern Generation (ATPG) tool uses deterministic test pattern generation when it creates a test pattern intended to detect a given fault. The ATPG Tools are a complete suite of software tools used to produce test patterns and gather diagnostic data for electronic assemblies including boundary scan devices.
Types of ATPG Algorithm
The DFT in VLSI approaches and test generation becomes substantially more difficult for sequential circuits than combinational circuits. This is because internal flip-flops and latches have controllability and observability difficulties. The ATPG algorithms are used for combinational and sequential circuits. Based on the presence of nonscannable flops in the design the ATPG is widely categorized into two categories:
- Combinational ATPG
- Sequential ATPG
The different ATPG algorithms used are:
- D Algorithm
- PODEM
- FAN
Stages of ATPG Algorithm:
The ATPG algorithm is a two-stage technique.
Pattern Generation for Random Tests:
In this strategy, we generate test patterns at random and pick those that discover undetected flaws. There is no target mistake. Because test patterns are developed by trial and error, this is a relatively quick and inexpensive procedure. It’s like throwing darts while blindfolded with a slew of targets around.
Generation of Deterministic Test Patterns:
In this strategy, we choose a specific target defect and use algorithms such as D, PODEM, or FAN. It is a time-consuming algorithmic process that is also more costly than Random TPG.
The Random TPG concept is that there are numerous easily detectable flaws. As a result, we perform Random TPG first, which is a faster process than the time-consuming Deterministic TPG. The issue with Random TPG is that when simple problems are found, fault coverage saturates. Deterministic TPG is only used for defects that are missed by Random TPG. These are sometimes referred to as random pattern-resistant defects.
The efficacy of the ATPG in VLSI determines the amount of fault coverage gained and the cost of completing the test (algorithm complexity and test length).
The ATPG Algorithm follows the following steps:
- Fault Activation
- Fault Propagation
- Line Justification
Benefits of ATPG in VLSI:
These are some of the benefits of ATPG in VLSI that have made it popular in the EDA industry:
- It generates high-coverage test patterns;
- Reduces test time and cost;
- Reduces human effort; and
- Ensures simple, risk-free deployment into design and test flows.
To sum up, ATPG alleviates our agony in circuit test pattern development. If appropriate fault coverage is attainable, we may need to integrate an incomplete ATPG algorithm in extreme instances.
Conclusion
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