Congestion in VLSI Physical Design Flow

As the number of transistors on a device grows, so does the design complexity. As a result, physical design plays a critical part in the VLSI design flow. When the number of routing tracks available for routing in a given location is less than the number necessary, the area is considered congested and hence, is termed as congestion in VLSI Physical Design Flow. The number of nets that may be routed through a given region will be limited. The floorplan stage of a VLSI design is critical for determining the chip’s area, size, and form. It is an iterative procedure to create a floorplan. When the designer is thorough with the floorplan, the next step is to run placement and optimization; once this is done, the designer will analyse the congestion map, cell density, and time reports before going on to the next stage of Clock Tree Synthesis.

What are the causes of traffic congestion in VLSI?

High standard cell density in a limited region;
Standard cells near macros;
High pin density at the edge of macros;
A poor floor plan;
IO optimization tool buffers, resulting in a large number of cells in the core region.

How Do You Get Rid of Congestion in VLSI?

Run the rapid placement using the congestion-driven option a second time (congestion drive placement).
Adjust cell density in busy regions to alleviate physical constraints. As a result of the increasing cell density, there is more congestion.
Use/modify appropriate obstructions, such as soft and hard blockages, as well as macro padding (halos) at appropriate areas to reduce congestion around macros.
In PnR tools, cell padding refers to the placement clearance provided to standard cells. This is usually done to relieve placement congestion or to set aside some space for later usage. Cell padding is commonly applied to the buffers/inverters used to form the clock tree, for example, so that room is allocated to insert DECAP cells near them following CTS.
Adjust floorplanning by shifting macros, changing core shape/size, and moving pins to make place for routing.

The VLSI Physical Design may become un-routable if the congestion is too severe. This is not a good situation. Hence, before proceeding, it is critical to reduce or remove the congestion.

Floor planning Process for Congestion in VLSI

The first phase in the physical design process is floorplanning. The primary goal of floorplanning is to determine the best position for each module on the layout surface based on interconnectivity. One key check to make while selecting the locations is that there should be no overlap between two modules. At the floorplan stage, the designer decides the size of the die and constructs wire tracks for typical cell arrangement. A power ground connection is made, and the position of the I/O pad/pin is determined.

At the floorplan stage, the designer should do sanity tests. The main goal of the layout is to:

Reduce the amount of space available.
Keep the entire wire length to a minimum.
Enhance routability.
Minimize the amount of time spent waiting.
Cut costs as much as possible

PnR Tool seeks to improve data path during placement and optimization so that data arrival time is decreased and worst negative slack (WNS) and total negative slack (TNS) are reduced. The process of identifying an appropriate physical position for each cell in the design is known as placement. The location has a big impact on the quality of routing in design. When a large number of cells are packed into a compact space, the number of routing tracks available for routing is less than the number necessary, resulting in design congestion in VLSI.

Importance of Floorplanning for Avoiding Congestion in VLSI:

Floorplanning is a key and important element in the PnR process. If the floorplan quality is poor, it can lead to difficulties such as traffic congestion, time violations, routing errors, and IR drop, among others. Only a few real-world design scenarios have been covered. To regulate congestion and lower cell density in the given region, feedthrough ports must be placed in the suitable location. In order to apply the appropriate technique for resolving I/O time problems, the true reason must be identified.

One technique for dealing with I/O time problems at the design stage may be to create bounds. This would also help the tool reduce the amount of buffers/inverters it inserts for I/O timing route optimization. The bound’s size and position should be carefully chosen by the designer. Depending on the situation, many boundaries can be added to the design.

Conclusion

There are many institutes which provide physical design course for beginners, including ChipEdge. There are several VLSI training institutes in Bangalore too where you can take online as well as offline VLSI courses which includes VLSI physical design course, DFT course and many more. Chipedge, being one of the best VLSI training institutes in India, offers a variety of courses that will equip you with the necessary skills required for getting a good job, as it uses great synopsys tools along with the lectures provided by experienced teaching faculty and also providing students access to the online VLSI lab and also placement assistance without any extra cost.