A system Verilog testbench is a container in which the design is placed and directed by various input stimuli. The created stimulus should be used to drive the design inputs. System Verilog Testbench or Verification environment is used to validate the functional correctness of the Design Under Test (DUT) by producing and driving a predetermined input sequence to the design, recording the design output, and comparing it to the expected output.
The verification environment is a collection of classes that execute certain operations, such as creating stimulus, driving, monitoring, and so on, and those classes will be named on the basis of the operation.
What are the components of a SystemVerilog testbench?
The Transaction is a class that holds a structure that is used to communicate with DUT. This class aids with top-level executions, offering critical information about the created stimulus to the coverage model.
The generator is responsible for generating the stimulus (the transaction class is created and randomly assigned) and sending it to the driver.
It receives the transaction from a generator and pushes the packet-level data inside the transaction into the pin level (to DUT).
It observes pin-level activity on interface signals and translates it to packet-level data, which is then delivered to components such as the scoreboard.
Data items are received from monitors and compared to predicted values.
Expected values might be golden reference values or values created by the reference model.
An agent is a container class that groups the classes (generator, driver, and monitor) that are particular to an interface or protocol.
The environment class serves as a container for higher-level components such as agents and scoreboards.
The test is in charge of,
- Setting up the testbench
- Starting the process of building testbench components.
- Initiating the stimulation driving.
This is the file at the top that connects the DUT and TestBench. It is made up of DUT, Test, and interface instances, with the interface connecting the DUT and the TestBench.
What’s the purpose of the system Verilog testbench?
System Verilog testbench allows to
- Create several sorts of input stimuli
- Use the created stimulus to drive the design inputs.
- Allow the design to handle input and produce results.
- Compare the output to the expected behavior to identify functional flaws.
- If a functional bug is discovered, modify the design to correct the problem.
Also Read Know the difference between Verilog and Systemverilog
Repeat the preceding procedures until there are no more functional faults.
Suppose, if the input is 10 bits and we wish to test all possible input values, i.e. 210-1 it is difficult to do so manually. In such instances, test benches are quite beneficial; also, tested designs are more dependable and preferred by clients. Furthermore, we may utilize test benches to get the results in the form of csv (comma-separated file), which can be used by other software for further analysis, such as Python, Excel, and Matlab, among others.
Because test benches are solely used for simulation (not synthesis), the complete set of Verilog constructs, such as keywords ‘for’, ‘display’, and ‘monitor’, may be used to write test benches.
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