Advanced eXtensible Interface or AXI is an on-chip communication bus protocol. It was developed by ARM. It is described by the Advanced Microcontroller Bus Architecture 3 (AMBA-3) and revisions were added in (AMBA-4) standards. The AXI is a point-to-point interface, designed for high-performance, high-speed microcontroller systems. The AXI protocol is based on a point-to-point link, which eliminates bus sharing and allows for more bandwidth and reduced latency. AXI is the most popular among all AMBA interface interconnects. It provides a basis for how different blocks inside each chip communicate with one another. The handshaking mechanism ensures that data is transferred in a clear and uninterrupted way. This allows various components to communicate without any interference.
What Exactly is an Advanced eXtensible Interface in an FPGA?
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The Advanced eXtensible Interface (AXI) is a protocol for communication between IP blocks designed for FPGAs based on AMBA. Here are some of the key characteristics of an AXI interface:
- It allows for burst transactions with simply the start address issued.
- The data and addresses go through different channels.
The AXI protocol, which was initially created for high-frequency systems, was designed to suit the interface requirements for a wide range of components while providing flexibility in how those components are coupled. AXI is created for high-frequency, low-latency designs. It is also backward compatible with AHB and APB from prior AMBA revisions.
The Advanced eXtensible Interface Architecture
The AHB (Advanced High-Performance Bus) is a single-channel bus used by several slaves and masters to exchange data. A priority arbiter decides which master gets to use the bus currently, while a central decoder handles slave selection. Operations are carried out in bursts that might take several bus cycles to complete. Every burst transmission comprises an address and control phase followed by a data phase.
Also Read All About The Advanced High-Performance Bus
AXI follows a similar principle, except it employs several, dedicated channels for reading and writing. AXI, like its predecessor, is burst-based and uses a similar address and control phase before data interchange. Out-of-order transactions, unaligned data transfers, cache support signals, and a low-power interface are some additional features of AXI.
Data transfer between Master and Slave following AXI protocol specification:
- The master and slave must “handshake” to authenticate valid signals.
- Transmission of the control signal must be in distinct phases
- Separate channels for signal transmission
- A continuous transfer may be achieved through burst-type communication
Conclusion
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