What are Isolation Cells in VLSI?

Isolation cells in VLSI are extra cells introduced by synthesis tools to isolate buses/wires crossing from a circuit’s power-gated domain to its always-on domain. The isolation list is a list of all the buses or wires that require isolation cells. We provide the clamping value of the nets in the isolation list as logic 0 or logic 1, and the synthesis tool inserts isolation cells appropriately.

Why Do We Require It?

When we clamp a wire to value 0, the synthesis tool typically inserts an AND gate with one of its inputs coupled to an isolation enabled signal from the Power Management Unit (PMU) inside the VLSI design. When we clamp a wire to value 1, the synthesis tool inserts an OR gate with one of its inputs linked to the inverted form of the isolation enabled signal. Isolation cells are made up of tool-inserted AND and OR gates.

Since the PMU regulates all power gating within a design, it enables the isolation enable signal prior to power gating to ensure that no ‘X’ value is communicated to the aon-domain once power is turned off. The isolation enable signal, isol pgd en as an active low signal.

Isolation cells are employed to separate domains. Consider that your design has two domains, D1 and D2. Domain D1 is in power shut down mode, whereas Domain D2 is in active mode. Because Domain D1 is in a power down state, erroneous logic might be propagated to Domain D2. To prevent this, isolation cells are placed between the domains to clamp a known value at the domain’s output when domain D1 is in shut down mode. Isolation cells should always be put in the same domain to perform their purpose (clamp the known value to the other domain).

Isolation Cell Logic Design

In a low power design, we may turn off major portions of the chip’s power, leaving only one or a few blocks powered on. To avoid floating input pins in a powered block, isolation cells must be used to connect input pins to logic ‘0’. We also refer to isolation cells in VLSI as clamp cells.

An isolation cell is necessary in low power architecture when each logic signal passes from a power domain that can be turned down to a domain that cannot be powered down. When both the input and output sides of the cell are turned on, the cell acts as a buffer, but it gives a steady output signal when the input side is turned off (prevents short circuit current due to floating nodes that are always on block). The cell’s operational mode is controlled by an enable input.

An enabled level shifter cell is one that can perform both level-shifting and isolation tasks. This cell is used when a signal passes from one power domain to another, when the voltage levels are different and the first domain can be turned off.

There are Level Shifter cells(low-level and up-level shifters) which are used to change the voltage range of a signal from one voltage domain to another. When the semiconductor is working in various voltage domains, this is essential. The voltage range of a signal in one voltage domain may differ from that of a signal in another voltage domain. The discrepancy in voltage range may cause the destination domain to work in an unreliable manner. Hence In the voltage domain crossings, level shifter cells are used.

Where Are Isolation Cells Placed?

Before power is turned off, the outputs of blocks that are being powered down must be isolated, and they must stay isolated until the block is fully powered up. Isolation cells in VLSI, are often located between two power domains and connect domains that are shut off to domains that are still switched on.

Conclusion

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