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Overview:

This course is designed for Verification  / RTL Design Engineers, who have worked/working on Verification and interested to learn System Verilog, UVM.  The course is designed as per current industry requirements and will be delivered by Senior Engineer with 15+ years of Design Verification Experience.

Importance is given to cover the concepts and methodology thoroughly with proper emphasis on hands-on labs, with at least 50 % time allocated to lab sessions.

Training Delivery Model:

  • Lecture & Lab sessions go hand in hand, like corporate training.
  • Sessions will be interactive.

Training Material & Certification:

  • Handouts of training material will be provided.
  • Course completion certificate from ChipEdge.
  • Course learning will be assessed as per Bloom’s Taxonomy.
  • Credits leading to M.S degree and Certification from Global University of Engineering, USA.

Who Can Attend This Course:

  • Verification / RTL Design / FPGA Engineers, who have worked or are working in Verification using Verilog or/and have used VERA/Specman etc. in the past and want to upgrade their skill set to Advanced Verification languages and methodologies.
  • Faculty working in Engineering Colleges / Universities, teaching VLSI subjects.

Pre-requisites:

  • Good knowledge on Verilog
  • Knowledge of Basic Verification flow.
  • Knowledge of ASIC / SOC design flow

Course Content Outline:

PART-I – Basic Course

Module 1:- Introduction to System Verilog:

Overview of HDL and HVL, Need for SystemVerilog, SV capabilities and highlights, SV as one solution HDVL.

Module 2a: System Verilog Basics

Lexical Conventions, Data types, Aggregate Data types, Casting, SV operators and their precedence. Processes, Understanding the Procedural statements and control flow, process execution threads and Fine Grain process controls. Interfaces and Modports, Virtual interfaces, Clocking blocks

Module 2b: Design and verification building blocks 

module, program, interface, subroutines, packages, configurations, compilation and elaboration, declaration namespaces, Simulation time, time units and time precision

Module 3:- SV Classes and Randomization and constraints:

Classes, objects, handles and built-in methods for efficient TB development. Efficient memory management in SV. Different randomization techniques and constructs. Inline randomization, seeding, random methods, and random stability.

Module 4: Riding SV on Chariot of OOPs.

Tasks and functions and their enhancements in System Verilog. Introduction to OOP concepts of data abstraction, data encapsulation, data hiding, inheritance, and polymorphism.

Module 5:- Coverage-based Verification 

Introduction to code and functional coverage. Functional coverage in SV. Cover groups, cover points, cover bins, and cross-coverage constructs. Different ways of sampling the coverage and measuring the verification closure.

PART-II – Advanced Course

Module 6:- Specialized communication packing and bug isolation in  SV:

Interprocess Synchronization and communication – Semaphore, Mailboxes and Named Events, Scheduling semantics Event-based simulation scheduling semantics— SystemVerilog’s stratified event scheduling algorithm— Determinism and non-determinism of event ordering— Possible sources of race conditions— PLI callback control points

Module 7:- Faster verification using System Verilog Assertions:

Introduction to Assertions. Advantages of assertions. Immediate and concurrent assertions. Writing assertion Sequences, Different ways of writing assertions and its constructs and calling methods.

Module 8:- Application Programming Interfaces 

Introduction to DPIs, DPI layers, importing and exporting mechanism from System Verilog to another language. Usage and advantages of using DPIs and its Limitations.

Tools to be used:

  • Synopsys Verification Tool Suite
  • Additional Lab Hours through VPN, to enable you to spend more time on labs from home. This is on top of the Trainer led lab sessions during class.

Assessment & Certification:

  • Course completion certificate from ChipEdge.
  • At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
  • Certification and Course Credits leading to M.S.Degree from Global University of Engineering, USA.

Trainer:

The trainer is a working professional with hands-on VLSI Verification and training experience of 19+ years.

The trainer is passionate about teaching and has mentored many engineers, both freshers as well as experienced professionals to help them improve their skills, knowledge, and performance. Having led multiple complex projects, she is well abreast of the evolving requirements of the industry.

She is passionate about sharing her knowledge and experiences and at the same time is an excellent communicator who enjoys the challenges of teaching and mentoring the new generation.

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