What is Clock Domain Crossing (CDC) and How Does it Work?

In digital electrical design, the process of moving a signal or vector (multi bit signal) from one clock domain to another clock domain is called clock domain crossing. It is the traversal of a signal in a synchronous digital circuit from one clock domain to another.

A digital circuit containing flip flops is generally related to clocks, and circuits with only one clock domain. With so many dedicated data processing islands in current SoCs, data must be transferred across these different clock zones (islands). When data is transmitted between two distinct clock domains, the new clock domain will appear to be asynchronous.

To comprehend Clock Domain Crossing (CDC), we must first grasp some fundamentals:

What are the Basics of Clock Domain Crossing (CDC)?

A clock domain is a section of the design that is driven by one or more clocks that are coupled to one another. A clock with a frequency of 10MHz is handled as a single clock domain design, as a half clock is powered by a 10MHz clock. Multiple clock domain designs, on the other hand, are those that contain two unrelated clocks (different clock frequencies) or clocks from two distinct sources (even if they have the same frequency).

What is a Synchronous System?

A synchronous system consists of a single electrical oscillator that creates a clock signal, as well as its clock domain, which includes the memory elements directly timed by the oscillator’s signal and the combinational logic coupled to the memory elements’ outputs.

The size of a clock domain in such a synchronous system is inversely proportional to the frequency of the clock due to speed-of-light delays, timing skew, and other factors. All of the digital logic in early computers was often run in a single clock domain. Because it is difficult to carry digital signals above 66 MHz on standard PCB traces due to transmission line loss and distortion (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that are almost always single-chip CPUs with a phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip.

Meta stability:

It is an important aspect to consider when dealing with multi-clock architectures. Meta stability is defined as an unstable or intermediate condition in layman’s words. When applied to the realm of digital design, this indicates that an FF can enter a condition where the output may not have attained its ultimate intended value and can oscillate between 0 and 1. After some time, the signal will stabilise, however this is dependent on the FF type and PVT circumstances.

Metastability is unavoidable in digital design, although it may be mitigated by employing various Clock Domain Crossing (CDC) approaches to ensure that the system’s functionality is preserved. In order for the flip flops to work properly, the inputs and clocks must meet the FFs’ setup and hold criteria.

Techniques for Clock Domain Crossing (CDC):

Synchronised Circuits: Synchronizer circuits are one of the most frequent ways to tackle Clock Domain Crossing (CDC). The goal of synchronizer circuits is to safeguard downstream circuitry from becoming metastable by lowering the chance of metastability and increasing the MTBF. A twin flip flop synchronizer is one of the most basic synchronizer circuits (also called 2-FF synchronizer).

Frequency: Distinct clock domains have clocks with separate frequencies, phases, or both (owing to varying clock delay or a different clock source). The relationship between the clock edges in the two domains cannot be trusted in any case. By registering a single bit signal through a flip-flop that is timed by the source domain, the signal may be synchronised to a higher frequency clocked destination domain.

In contrast to reset domain crossover metastability, which may happen between synchronous and asynchronous clock domains, CDC metastability concerns can happen between asynchronous clock domains.

Conclusion

Traditional verification approaches such as simulation and static timing analysis are insufficient to discover all sorts of clock domain crossover concerns. The sorts of clock domain crossovers that might cause difficulties vary. Similarly, the solutions to those issues change, and as a result, the verification methodologies required varies.

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