What is Metastability in VLSI and How to Avoid it? -

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# What is Metastability in VLSI and How to Avoid it?

Metastability in VLSI is an unstable equilibrium occurrence in digital electronics in which the sequential element is unable to resolve the state of the input signal. This causes the output to remain unresolved for an infinite period. This often occurs when data transitions extremely close to the active edge of the clock, breaking setup and holding constraints. Because the data transitions near the active edge of the clock, the flop is unable to catch the data entirely. The flop begins to capture data, and the output begins to transition. However, before the output changes its state, the input is disconnected from the output when the clock edge arrives.

## How Does Metastability in VLSI Occur?

When there is setup and hold time violations in a flip-flop, it enters a state in which its output is unpredictable: this is known as a metastable state (quasi-stable state). At the end of the metastable state, the flip-flop settles down to either ‘1’ or ‘0’. This is referred to as metastability.Â  When the flip-flop is in a metastable state, the output oscillates between ‘0’ and ‘1’. The time it takes to settle down is determined by the technology of the flip-flop.

## How To Avoid Metastability In VLSI?

In reality, it is impossible to prevent metastability without the employment of complex self-timed circuits and increasing clock-to-Q delays when synchronizing asynchronous inputs. Designers can tolerate metastability in the simplest instance by ensuring that the clock period is long enough to allow for the resolution of quasi-stable states and the delay of whatever logic is in the route to the next flip-flop. This strategy is rarely viable given the performance needs of most current systems.

Tolerating metastability in VLSI is most commonly accomplished by adding one or more subsequent synchronizing flip-flops to the synchronizer. This method permits metastable events in the first synchronizing flip-flop to resolve themselves across a complete clock period. However, this increases the delay in the perception of input changes of the synchronous logic. Neither of these systems can ensure that metastability will not pass through the synchronizer. They only lower the likelihood to manageable levels.

## Conclusion

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