Design For Test Online (Self-Paced)
Design For Testability, commonly called as DFT is a specialization in the SOC design cycle, which facilitates design for detecting manufacturing defects. DFT is different than functional verification, which tests the functionality of the design and is popularly known as Design Verification.
DFT has evolved as a specialization in itself over a period of time, with the increase in size & complexity of chips, facilitated by the advancement of manufacturing technologies like 10nm, 7nm, DFT Engineers works on introducing various test structures as part of the design flow, on increasing the testability of logic, pads, memories, interconnects.
Online DFT Course covers different techniques like Scan Insertion to test the combinational & sequential logic, BIST to test the memories, JTAG to test the PADS..etc. Using ATPG Techniques test patterns are generated on the scan inserted design. Generated patterns are simulated and debugged in case of any failures.
|Topic No.||Topic Name||Course Contains|
|Topic 1||DFT and SCAN Basics||6 lecture, 2 Lab – 04:25:00|
|Topic 2||Scan DRC and Scan stitching – 1||6 lectures, 2 Lab – 03:54:00|
|Topic 3||Scan DRC and Scan stitching – 2||6 lectures, 2 Lab – 05:48:00|
|Topic 4||Lock up Latch and Clock gate Concepts||3 lectures, 2 Lab – 03:49:00|
|Topic 5||SCAN Compression||3 lectures, 2 Lab – 04:00:00|
|Topic 6||JTAG and Boundry SCAN||6 lectures, 2 Lab – 06:34:00|
|Topic 7||DFT and ATPG Basics||5 lectures, 2 Lab – 06:25:00|
|Topic 8||Fault models, Stuck-at ATPG, ATPG DRC||9 lectures, 2 Lab – 07:37:00|
|Topic 9||ATPG Pattern simulation and debugging||5 lectures, 1 Lab – 03:21:00|
|Topic 10||At-speed ATPG , At-speed pattern simulation & Diagnosis||5 lectures, 2 Lab – 05:08:00|
|Topic 11||BIST and Memory Testing||3 lectures, 1 Lab – 03:44:00|