Physical Design Course for Freshers I Job Oriented VLSI Training

                                                  Admissions are in progress for PD, DFT, RTL Design and ASIC Design Verification Courses

Physical Design Course – For Freshers

Kick Start your VLSI Career by Joining this Placement Assisted Course, Designed as Per Industry Skill Requirements and Delivered by Industry Experts. Using Synopsys Tools Design Compiler, ICC2, Prime Time, IC Validator, StarRC.

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  • Integrated Internship

  • Synopsys Tools

  • 100% Money Back Guarantee

  • 24x7 VLSI Lab Access

  • 100% Placement Assistance

  • Start Date14th August 2021
  • Duration:22 Weeks
  • Training Type Instructor Led Live Online

Course Overview

Physical Design Course is designed for fresh graduates looking to get comprehensive training needed to start a career in the VLSI industry as a Physical Design Engineer. The course is designed by keeping the latest industry requirements in mind and will be covered by trainers experienced in Physical Design. All the relevant concepts, the latest methodologies, the support functions required as well as placement specific coaching will be provided over the duration of the course.  Up to 70% of the time will be utilized for hands-on training along with multiple projects.  

Course Fee

70,999 100,000

29% Covid Discount. Exclusive of GST


  • No Cost EMI option
  • 100% Money Back Guarantee
  • Group Discounts

Speak to our Learning Advisor for details.

Delivery Model:
  • Each topic is followed by hands-on lab sessions with VLSI tools (Synopsys Tools).
  • Closed group support with Trainers and Lab Assistants on Whatsapp and email tech groups.
  • All sessions (Lecture & Lab) will be recorded to view at a later time.
Duration & Timings:

For Freshers: (22 weeks – Hybrid Model)

  • 16 weeks – Physical Design Course
  • 6 weeks – VLSI foundation modules on Linux, Digital design, CMOS fundamentals, Verilog and TCL scripting.
  • 9:30 am to 1 pm, Saturday & Sundays
  • 9:30 am to 5 pm, Tuesday – Friday (Trainer assistance on Labs, assignments, projects &  Self practice)
  • These timings are in IST (Indian Standard Timing) time zone.
  • Monday – Holiday


  • The course will be delivered by a Senior VLSI Engineer with lab assistance from a junior VLSI Engineer. Both are currently working in the VLSI industry on the latest technologies.
  • Trainers with 10+ years of Physical Design experience in Industry.
  • Synopsys Design Compiler, IC Compiler 2 (ICC2), starRC, and Primetime tools.
  • The course is designed by experts in Physical Design, as per the needs of the industry.
  • 70% of the course time on labs, to facilitate hands-on learning using tools.
  • Soft skills training by leading corporate soft skill trainers.
  • Mock Interviews from the Senior  Industry Professionals.

VLSI Tools & Lab

Synopsys Tools:
  • Digital Design with Verilog:  VCS.
  • Synthesis – Design Compiler Topographical.
  • Static Timing Analysis(STA): Prime Time SI.
  • Physical Design:  IC Compiler 2 (ICC2).
  • RC Extraction: Star RC.
  • Physical Verification: IC Validator
Technology Libraries To be Used:
  • 14nm FINFET Libraries
Lab Access:
  • Flexible learning with online 24×7 lab access running on high-end cloud servers
  • Access VLSI Lab anytime anywhere using VPN

Who Can attend this Course

  • Graduate Freshers(B.E/ in ECE/EEE/Instrumentation/Telecom who have graduated in 2019 or later.
  • Post-Graduate Freshers (M.Tech) with specializations like VLSI/Embedded/Power Electronics Communications/Instrumentation etc. who have graduated in 2019 or later?
  • Experienced Engineers / Faculty who have graduated in 2018/ earlier, but have some industry (any) / teaching experience and interested to switch to the VLSI industry.

Placement Assistance

Chipedge provides placement support as a complimentary service until the candidate gets the job.  Help on Resume preparation, mentoring, softskills will be provided.

Why Choose ChipEdge ?

Latest VLSI Courses

An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.

Industry experts trainers

A meticulous and stringent selection process in handpicking the best trainers from the industry with good experience & currently working on latest technologies.

Latest Synopsys tools

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Individual attention

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning Management system

Multiple Learning Models to choose as per your Learning Needs & budget in most cost effective way.

24x7 Lab access

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24x7 availability


Linux introduction, File structure, Commands: PWD, ls, cd, mkdir, rmdir, rm, mv, cp, cat, more, less, head, tail, ps, kill, date, uptime, whoami, df, du, chmod, grep, pipes. Introduction to GVIM & practice of commands.

Device Characteristics, Power Sources, Thevenin’s and Norton’s theorem, Semiconductor Device Physics. BJT, MOSFET : Working and I-V Characteristics. CMOS : Logic Gates and Boolean Expression Implementation, Stick Diagram, CMOS Logic Gate Parameters

Semiconductor Processing Methods, Second Order Effects in CMOS Technology.

Number Theory, Boolean Algebra, K-map, Combinational circuits, and Sequential circuits.

Overview of Digital Design with Verilog HDL, kinds of modeling styles: gate-level, dataflow, and behavioral. Language Constructs and Conventions. Few programming examples.

Review of ASIC Design flow & role of Synthesis, Synthesis flow, writing timing constraints in SDC format, constraining the design for timing, power, area goals, set optimization techniques, synthesize the design, Low power synthesis using UPF, generate and analyze the reports, save the netlist, SDC and interface files.

Formal Verification, Understanding & Matching compare points, Debugging nonequivalent points, What-If Analysis.

Introduction to TCL, TCL commands, Variables, special characters, arithmetic expressions, regular expressions, Procedures, conditional branching: if-then-elseif, switch, looping: for, foreach, while, Break and continue. Working with lists and arrays.

Scripting exercises from simple problem to complex automation problems, in an incremental manner and using the tools like Design Compiler, Prime Time, ICC2.

Introduction to the physical design, Physical Design Flow,

Data preparation: Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input, Sanity checks.

Goals of Floorplanning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines, channel-width estimation

Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power consumption. Why Low power and low power techniques. Electro-migration analysis.

Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.

STA Overview and concepts, Basic timing checks (setup, hold), understanding timing constraints(SDC), timing corners, timing report analysis,

General optimization techniques, typical causes for timing violations, and strategies for fixing the same, Pre-CTS optimization to Fix setup violations.

Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,

Post-CTS optimization : Fixing Setup and Hold violations

Goals of Routing, Stages of Routing: Global Routing, Track assignment, and Detail Routing, Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.

Post layout STA using SPEF, Multi-Mode Multi Corner STA, Derating factors, PVT, OCV, AOCV & POCV Variations, Crosstalk & Noise Analysis.

What is ECO, Types of ECO, Timing & Functional ECO prep, Performing the ECO placement, and routing?

Physical Verification (DRC, LVS, ANT, ERC, DFM), STA, IR drop analysis, Electro-Migration Analysis.

Projects will be given a converging Netlist to GDS II flow. Various projects that will allow the students to understand the intricacies of implementation for the minimum area, low power, high performance. The method of execution will be similar to a typical block-level Physical Design work/project in the industry. Block-level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks

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Demo Videos

Video Reviews

Learner Reviews

I Have done Physical design course in ChipEdge. Mostly all the concepts I learned through practical labs with the help of trainers. Trainers are from product based company with more than 10 years experience. One Good thing is, they have provided individual license for all to practice the tool, which has VPN facility. Through ChipEdge placement assistance I got placed in Moslogi.

Ajay Batula

My expectation to join this course was to get into PD domain and Yes, it met my expectations. Trainer is excellent and he answered all types of queries I asked. Materials provided are good and helped to crack the interviews. After doing this course it helped me to get into PD domain.

Haritha Mohan

My expectation to attend this course was to explore my carrier in VLSI (Physical design) as I have completed my master in VLSI. Trainer used to teach what industry needs. Course overall is good and it met my expectations.

Sanjay Chauhan


The Minimum Qualification Required Is An Educational Background In Electronics.  This Could Include

  • B. Tech/B.E In ECE / EEE / Telecom / Instrumentation.
  • M.Tech/M.Sc In VLSI / Embedded / Power Electronics / Digital Electronics / Digital Communications.

Year of Passing:

  • For freshers without job experience:  2019 / 2020
  • For Engineers with experience in some domain:  2018 or earlier.


one should have 60% or above percentage throughout the academics

Admission into Job Oriented Courses is a two-stage process:

    1. Written Test – you need to attend an online test, which tests your knowledge on fundamentals like digital electronics, CMOS, aptitude..etc. you need to score 60% to qualify for the technical interview.
  • Technical Interview – Our technical experts will take your interview on a video call, to assess your fundamentals knowledge and suitability for the VLSI field. you will be selected for admission, subject to your performance in the interview.

For more information, please visit the admission process 

Considering the covid19 pandemic, we have converted the job oriented courses with regular classroom training to a blended learning model.

For 4 months, you will attend the instructor-led online classes from home, including labs. For 5th month, you can come to Bangalore for doing project if covid19 situation improves. Else you can complete the project online. Its upto your choice.

Except changing the delivery model to blended, everything else remains the same ..which includes duration of the course, syllabus, faculty,  labs, projects, placements.

As we are taking only 40 seats per the course, you will get same care and attention from the faculty, which you get in class room learning.

All Our Trainers Have 10-20 Years Of Experience In The VLSI Industry. They Are Selected For Their Domain Expertise, Passion For Sharing Knowledge As Well As Excellent Teaching Skills.

We Provide Placement Assistance By Arranging Interview Opportunities With Hiring Companies. This is a complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.

Every Learner Gets up to 5 Interview Opportunities To Prove their Ability. To Ensure Successful Placement, We Provide Added Support Including Mentorship, Fundamentals Classes, Soft Skills Training, Mock Interviews Etc.

We provide comprehensive placement assistance, but we do not give any placement guarantee.  We provide quality training and interview opportunities to all our learners;  but how you utilize the opportunities and crack the interviews will solely depend on you.

As per our knowledge, most of the training organizations/colleges, even premium colleges like IITs/NITs/IIMs, they do not guarantee the placement. As per the reputation of the organization, companies do visit for hiring and candidates gets jobs. It depends on the candidates, how they utilize the campus for learning and proving his/her talent, when opportunity is given. 

Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In-Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 12.5 Lakhs.

Each year many companies visit ChipEdge for recruiting the various positions because of the quality training that we offer. Both Service Companies like  Aricent, Altran, Sankalp Semi, Synapse, Cerium, Mindlance, Signoff Semiconductors Etc. as well as  Product Companies (MNCs) like include Intel, Samsung, Synopsys, MediaTek, Global Foundries, Microsemi …Etc visit us regularly for hiring. 


For a complete list of companies visit


Internship option available for students, integrated with the job-oriented course.

The Internship model has 2 phases.

Phase1 – Learning:  4 months

Learning respective domain knowledge in 4 months, along with hands-on labs with VLSI tools.

Phase2 – Application (Projects):  2 months

Application of your learning in projects. one project will be part of course work, which completes in 5 months.

Whoever chooses the internship option, the extra project will be provided for the 6th month along with lab access and guidance from the technical experts.  

For further details, please check with our Learning Advisor.

We use 28nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.


Providing real time projects is not feasible in a VLSI Training environment. The projects we provide are of similar complexity but of a medium size as executed in the industry. For Learning purposes these projects are good enough. Many working professionals & students achieved success, by working on these projects.

VLSI Companies send their engineers to chipedge, to get their engineers trained on these projects. 


We do have installment options for some courses. EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Learning Advisors. 

ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals. If you are not happy with the course quality, 100% of your fee will be refunded. 

Please visit the refund policy for more details.

Sorry, GST is mandatory for all course fee payments and tax invoice will be provided to you.. We follow the Govt Tax Laws strictly, as part of our corporate governance policy.

We understand 18% GST is significant amount. We have recommended Govt of India, to consider reducing the GST for skill development programs. We are hopeful, they will reduce in future.