Admissions open for next batch of weekend DFT, PD Courses
10% Early Bird Discount ( limited Offer)
Physical Design Course is designed for fresh graduates looking to get comprehensive training needed to start a career in the VLSI industry as a Physical Design Engineer. The course is designed by keeping the latest industry requirements in mind and will be covered by trainers experienced in Physical Design. All the relevant concepts, the latest methodologies, the support functions required as well as placement specific coaching will be provided over the duration of the course. Up to 70% of the time will be utilized for hands-on training along with multiple projects. Blended Learning Model: Learning (Theory + Labs) : 4 months (Online). Project (application of your learning): 1 month (Online / Class Room). Integrated Internship: 1 month (optional).
An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.
50% Hands-on Labs, Lab access during non class days and VPN Access to Tools from home.
A meticulous and stringent selection process in handpicking the best and most qualified trainers from the industry.
Limited seats in each batch to ensure individual attention for trainees both in classes and in labs.
The latest Synopsys Tools with individual Licenses for each trainee.
Customised Online platform for Content Delivery and Evaluations to achieve a seamless learning experience.
Linux introduction, File structure, Commands: PWD, ls, cd, mkdir, rmdir, rm, mv, cp, cat, more, less, head, tail, ps, kill, date, uptime, whoami, df, du, chmod, grep, pipes. Introduction to GVIM & practice of commands.
Device Characteristics, Power Sources, Thevenin’s and Norton’s theorem, Semiconductor Device Physics. BJT, MOSFET : Working and I-V Characteristics. CMOS : Logic Gates and Boolean Expression Implementation, Stick Diagram, CMOS Logic Gate Parameters
Semiconductor Processing Methods, Second Order Effects in CMOS Technology.
Number Theory, Boolean Algebra, K-map, Combinational circuits, and Sequential circuits.
Overview of Digital Design with Verilog HDL, kinds of modeling styles: gate-level, dataflow, and behavioral. Language Constructs and Conventions. Few programming examples.
Review of ASIC Design flow & role of Synthesis, Synthesis flow, writing timing constraints in SDC format, constraining the design for timing, power, area goals, set optimization techniques, synthesize the design, Low power synthesis using UPF, generate and analyze the reports, save the netlist, SDC and interface files.
Formal Verification, Understanding & Matching compare points, Debugging nonequivalent points, What-If Analysis.
Introduction to TCL, TCL commands, Variables, special characters, arithmetic expressions, regular expressions, Procedures, conditional branching: if-then-elseif, switch, looping: for, foreach, while, Break and continue. Working with lists and arrays.
Scripting exercises from simple problem to complex automation problems, in an incremental manner and using the tools like Design Compiler, Prime Time, ICC2.
Introduction to the physical design, Physical Design Flow,
Data preparation: Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input, Sanity checks.
Goals of Floorplanning, different aspects of floor planning, Rectangle/Rectilinear floorplans, Die size estimation (Core Utilization, Aspect ratio), IO placement, macro placement and guidelines, channel-width estimation
Goals of Power Routing, Power distribution structure (Rings, straps and follow-pin/std cell rail), metal stack information, power planning methodology, IR drop analysis, types of power consumption. Why Low power and low power techniques. Electro-migration analysis.
Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, placement optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Path Grouping and creating Bounds.
STA Overview and concepts, Basic timing checks (setup, hold), understanding timing constraints(SDC), timing corners, timing report analysis,
General optimization techniques, typical causes for timing violations, and strategies for fixing the same, Pre-CTS optimization to Fix setup violations.
Goals of CTS, Types of Clock-tree, constraints for CTS, building clock tree, Analyze the results,
Post-CTS optimization : Fixing Setup and Hold violations
Goals of Routing, Stages of Routing: Global Routing, Track assignment, and Detail Routing, Routing options, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guidelines for optimum routing results.
Post layout STA using SPEF, Multi-Mode Multi Corner STA, Derating factors, PVT, OCV, AOCV & POCV Variations, Crosstalk & Noise Analysis.
What is ECO, Types of ECO, Timing & Functional ECO prep, Performing the ECO placement, and routing?
Physical Verification (DRC, LVS, ANT, ERC, DFM), STA, IR drop analysis, Electro-Migration Analysis.
Projects will be given a converging Netlist to GDS II flow. Various projects that will allow the students to understand the intricacies of implementation for the minimum area, low power, high performance. The method of execution will be similar to a typical block-level Physical Design work/project in the industry. Block-level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks
I Have done Physical design course in ChipEdge. Mostly all the concepts I learned through practical labs with the help of trainers. Trainers are from product based company with more than 10 years experience. One Good thing is, they have provided individual license for all to practice the tool, which has VPN facility. Through ChipEdge placement assistance I got placed in Moslogi.
My expectation to join this course was to get into PD domain and Yes, it met my expectations. Trainer is excellent and he answered all types of queries I asked. Materials provided are good and helped to crack the interviews. After doing this course it helped me to get into PD domain.
My expectation to attend this course was to explore my carrier in VLSI (Physical design) as I have completed my master in VLSI. Trainer used to teach what industry needs. Course overall is good and it met my expectations.
The Minimum Qualification Required Is An Educational Background In Electronics. This Could Include
Year of Passing:
one should have 60% or above percentage throughout the academics
Admission into Job Oriented Courses is a two-stage process:
For more information, please visit the admission process
Considering the covid19 pandemic, we have converted the job oriented courses with regular classroom training to a blended learning model.
For 4 months, you will attend the instructor-led online classes from home, including labs. For 5th month, you can come to Bangalore for doing project if covid19 situation improves. Else you can complete the project online. Its upto your choice.
Except changing the delivery model to blended, everything else remains the same ..which includes duration of the course, syllabus, faculty, labs, projects, placements.
As we are taking only 40 seats per the course, you will get same care and attention from the faculty, which you get in class room learning.
All Our Trainers Have 10-20 Years Of Experience In The VLSI Industry. They Are Selected For Their Domain Expertise, Passion For Sharing Knowledge As Well As Excellent Teaching Skills.
We Provide Placement Assistance By Arranging Interview Opportunities With Hiring Companies. This is a complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.
Every Learner Gets up to 5 Interview Opportunities To Prove their Ability. To Ensure Successful Placement, We Provide Added Support Including Mentorship, Fundamentals Classes, Soft Skills Training, Mock Interviews Etc.
We provide comprehensive placement assistance, but we do not give any placement guarantee. We provide quality training and interview opportunities to all our learners; but how you utilize the opportunities and crack the interviews will solely depend on you.
As per our knowledge, most of the training organizations/colleges, even premium colleges like IITs/NITs/IIMs, they do not guarantee the placement. As per the reputation of the organization, companies do visit for hiring and candidates gets jobs. It depends on the candidates, how they utilize the campus for learning and proving his/her talent, when opportunity is given.
Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In-Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 12.5 Lakhs.
Each year many companies visit ChipEdge for recruiting the various positions because of the quality training that we offer. Both Service Companies like Aricent, Altran, Sankalp Semi, Synapse, Cerium, Mindlance, Signoff Semiconductors Etc. as well as Product Companies (MNCs) like include Intel, Samsung, Synopsys, MediaTek, Global Foundries, Microsemi …Etc visit us regularly for hiring.
For a complete list of companies visit https://chipedge.com/hiring-companies/
Internship option available for M.tech students, integrated with the job-oriented course.
The Internship model has 2 phases.
Phase1 – Learning: 4 months
Learning respective domain knowledge in 4 months, along with hands-on labs with VLSI tools.
Phase2 – Application (Projects): 2 months
Application of your learning in projects. one project will be part of course work, which completes in 5 months.
Whoever chooses the internship option, the extra project will be provided for the 6th month along with lab access and guidance from the technical experts.
For further details, please check with our Learning Advisor.
We use 28nm libraries for labs, projects.
We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.
This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.
Providing real time projects is not feasible in a VLSI Training environment. The projects we provide are of similar complexity but of a medium size as executed in the industry. For Learning purposes these projects are good enough. Many working professionals & students achieved success, by working on these projects.
VLSI Companies send their engineers to chipedge, to get their engineers trained on these projects.
ChipEdge believes in quality and professional approach in what we offer, which earned a reputation from industry & professionals. If you are not happy with the course quality, 100% of your fee will be refunded.
Please visit the refund policy for more details.
Sorry, GST is mandatory for all course fee payments and tax invoice will be provided to you.. We follow the Govt Tax Laws strictly, as part of our corporate governance policy.
We understand 18% GST is significant amount. We have recommended Govt of India, to consider reducing the GST for skill development programs. We are hopeful, they will reduce in future.