State of the art SOC designs is so complex that, coming up with a bug-free design is very difficult. So chip design flow incorporates several steps to identify the bugs in the earlier stages as well as, in the later stages.
Verification and Validation, both probe for the correctness of the design against the specification by identifying and localizing the bugs in the system, but at different stages in the design cycle. Verification is a pre-silicon process of checking the functionality of the design by simulating it whereas, Validation is a post-silicon process of finding bugs in a few initially manufactured prototypes in the context of a system.
Functional verification is the process of demonstrating the functional correctness of an RTL design with respect to the design specifications. Functional verification attempts to check whether the proposed design is doing what it is intended to do. This is a complex task and takes the majority of time and effort in most large electronic system design projects. It is imperative that the design is functionally verified and any potential bug is eliminated at an early stage.
It is very common that more engineers’ time and expense is spent to verify a design than the rest of the steps in the ASIC design cycle. Even with this large expenditure, most designs are first fabricated with several bugs still in them. So here comes the importance of Validation.
While pre-silicon verification runs the test cases on the design on the simulator, post-silicon validation is executed on a few initial hardware prototypes of the design on the silicon chip in a real environment. This process captures the bugs that are escaped during the RTL Design Verification phase. Validation also checks for the correctness of the design but on the real hardware in an actual working ambiance.
When a design is passed through all the steps in the design cycle, a few initial prototypes are fabricated as test prototypes. These prototypes are mounted on a test board in a real working environment with real test speed. Identifying bugs through validation is a very fast process as compared to the design verification process but it is difficult to debug the design as there is no way to access the internal signals.