MOS Operation, I-V Characteristics of MOS, Inverter Operation, Nand/Nor CMOS Circuits, MOS Second-order Effects, Overview of ASIC/SOC design flow and Overview of Physical Design online course flow.
- Introduction to Synthesis
- Synthesis Flow
- Constraining Design for timing, area & power
- Understanding Timing Library (.lib) format.
- Synthesize Design
- Timing Checks
- The report, Analyze and debug results
- Optimization Techniques
- Saving the results
List of inputs (libraries, technology files, netlist, timing constraints, IO placement) to the PD flow, Understanding the contents of each input file, qualifying the received inputs and sanity checks.
Goals of floor planning, different aspects of floor planning, Area estimation, Square/Rectangle/Rectilinear Floorplans, IO placement, macro placement, channel-width estimation, Floor planning guidelines.
Goals of Power Routing, Types of Power Routing, PG-Rings, PG Mesh and follow-pin/std cell rail.
Goals of Placement, types of placements, pre-place (End-cap, Tap & I/O Buffer) cells, , pre-place optimization and in-place optimization, congestion analysis, timing analysis, Tie-cells, High-Fanout Net Synthesis, Scan chain re-order, Regioning/Grouping/Bounds.
Basic timing checks(setup, hold..), understanding timing constraints(SDC), timing corners, timing report analysis, general optimization techniques, typical causes for timing violations and strategies for fixing the same.
Goals of CTS, Types of Clock-tree, CTS Specification, Building clock tree, Analyze the results, Fine-tuning the Clock-tree and Guidelines for best CTS results.
Goals of Routing, Types-of Routing, Global Routing, Detail Routing, Fixing of routing violations (DRC, LVS), post route optimization, issues in routing and guide lines for optimum routing results.
What is ECO, Types of ECO, Timing & Functional ECO prep, rolling in the ECO, Performing the ECO placement and routing.
Physical Verification (DRC, LVS, ERC), IR drop analysis, Electro-Migration Analysis, Cross-Talk (SI) analysis, Sign-off Timing analysis, Logical Equivalence checking.
2-3 projects will be given covering Netlist to GDS flow. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to complete routing, after cleaning all the issues during sign-off checks.