ASIC Design Flow
Introduction to Verification
Verification Flow
Testbench Architecture
Verification Plan
Verilog is pre-requisite for this course. However essential Verilog concepts needed for verification will be refreshed.
ASIC Verification Flow, Verilog Vs SystemVerilog, Testbench Architecture, Migrating from Verilog to System Verilog.
Operations with 4-state Logic, Arrays, Structures, Unions, packed, unpacked, tagged.
Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.
Fork-join and its controls, Semaphore, Mailbox.
Need for OOPs in testbench, OOPs Terminology, Principles of OOPs, Inheritance, Polymorphysim, Copy (Shallow/Deep copy), Specilized classes, parameterized classes.
Dynamic Arrays, Associative Arrays, Array methods and usage, Tips for scoreboard Development
Need for Randomization, Controlling randomization, Constraints, Inline Constraints, Controlling constraints.
Need of Methodology, Constrained Random Verification, Verification Concepts
UVM Class Library, UVM Testbench, UVM Test, UVM Environment, UVM Scoreboard, UVM Agent, UVM Sequencer, UVM Sequence, UVM Driver, UVM Monitor
UVM Class Hierarchy, UVM Factory, UVM Config-db, UVM Callbacks, Parameterizing, Transactions, Phases, Event-pool, Field-macros, Messaging, Components vs Object
Basic TLM Communications, Communication Between Processes, UVM Analysis Communication
Data Item for Generation, Transaction Modelling, Driver Implementation, Sequencer, Monitor, Agent, Scoreboard, Environment, Test case, Top module
Configuration Database, Virtual Sequence and Virtual Sequencer, Advanced Score boarding Techniques – decl Macros, RAL Model
APB/AHB Slave IP Verification
Ethernet 1G MAC VIP Development
