ASIC Verification Course | Design Verification Training | ChipEdge

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ASIC Design Verification Course

Learn ASIC verification course, the most in-demand skill set with high number of jobs in VLSI. The course is Designed & delivered by Verification Experts from VLSI Industry, with Live Online Classes on Weekends.

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  • Expert Trainers

  • Synopsys Tools

  • 100% Money Back Guarantee

  • 24x7 VLSI Lab Access

  • Placement Assistance

  • Start Date19th February 2022 (tentative)
  • Duration:16 Weeks
  • Training Type Live Online Classes

Course Overview

Design Verification (DV) is also called RTL / Functional Verification, which involves testing the Design for Functionality. Verification in VLSI is similar to testing work in the software industry. In any VLSI Project, the number of Design Verification Engineers is more than other skill sets. Hence a number of job opportunities is more for Verification Engineers. Trained DV Engineers are on demand most of the time. DV Engineers exhaustively test the design (RTL Code) for functionality and closely work with RTL Design Engineers to get the bugs fixed. ASIC Design Verification Course comprehensively covers digital design, Verilog for verification with multiple examples & projects, System Verilog & UVM along with labs & projects.  2 to 3 protocols will be covered during training and part of the projects. ASIC Design Verification Course is designed and delivered by practicing experts in Verification, as per the industry requirements.  Importance is given to cover the concepts and methodology along with a good emphasis on hands-on training. 60% of the course time is allocated to the guided lab sessions and industry-standard projects.

Course Fee

55,999 73,000

Exclusive of GST


  • No Cost EMI option
  • 100% Money Back Guarantee
  • Avail early bird discount up to 20%, Valid till 19th Jan 2022
  • Group Discounts

Speak to our Learning Advisor for details.

Knowledge of the below topics is Required.

Working knowledge of Linux.
Knowledge of Digital Design
Working knowledge of Verilog for verification.

You will be able to understand System Verilog, if have the above pre-requisite knowledge.  Online Test on Design Verification with Verilog need to be taken, to assess if you are meeting pre-requisite criteria.

If you do not meet, you need to ramp up using self learning materials/resources or live sessions if available. And take the test again.

Contact our learning advisor for taking the pre-requisite test.

Course Delivery Model

Live Online Sessions
Module-specific Lecture sessions and Labs conducted hand-in-hand
Emphasis on hands-on lab sessions aimed at building key skills
Weekdays: Lab support through WhatsApp
Flexible learning with Lab Access from home

Duration & Timings:

  • 16 weeks – ASIC Design Verification Course
  • 9:30 am to 1 pm, Saturday & Sundays
  • These timings are in IST (Indian Standard Timing) time zone.
  • The course will be delivered by a Senior VLSI Engineer with lab assistance from a junior VLSI Engineer. Both are currently working in the VLSI industry on the latest technologies.

VLSI Tools & Lab

Synopsys Tools

VCS Tool Suite.

Technology Libraries To be Used: 14nm Libraries

Lab Access:

  • Flexible learning with online 24×7 lab access running on high-end cloud servers
  • Access VLSI Lab anytime anywhere using VPN

Who Can Attend this Course

  • Working Professionals (including interns..) from the VLSI / Embedded industry who are currently working in areas like RTL Design, FPGA Design, Board Level Testing and would like to upskill on SV, UVM either  to perform better in current role or  switch your role / career to ASIC Design Verification
  • Professionals from IT / Electronics / Any other sector interested in switching to VLSI industry for career growth.
  • Faculty working in Engineering colleges interested to switch to VLSI industry.

Educational Qualifications

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar

No Cost EMI

Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months EMI without paying any additional cost on interest.


Monthly Option


3 Months


6 Months


9 Months


Placement Assistance

Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.

The Placement Desk has emerged as a favored destination for many organizations who come back year after year to recruit fresh talent nurtured at ChipEdge.

We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Why Choose ChipEdge ?

Latest VLSI Courses

An exhaustive bouquet of VLSI courses, from Design to Tape-out in both Analog and Digital domains.

Industry experts trainers

A meticulous and stringent selection process in handpicking the best trainers from the industry with good experience & currently working on latest technologies.

Latest Synopsys tools

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Individual attention

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning Management system

Multiple Learning Models to choose as per your Learning Needs & budget in most cost effective way.

24x7 Lab access

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24x7 availability


ASIC Design Flow
Introduction to Verification
Verification Flow
Testbench Architecture
Verification Plan

Verilog is pre-requisite for this course. However essential Verilog concepts needed for verification will be refreshed.

ASIC Verification Flow, Verilog Vs SystemVerilog, Testbench Architecture, Migrating from Verilog to System Verilog.

Operations with 4-state Logic, Arrays, Structures, Unions, packed, unpacked, tagged.

Need for Interface, Interface ports, mod ports, clocking, blocks, procedural blocks, Creating Instances, Connecting, DUT and TB via Interfaces.

Fork-join and its controls, Semaphore, Mailbox.

Need for OOPs in testbench, OOPs Terminology, Principles of OOPs, Inheritance, Polymorphysim, Copy (Shallow/Deep copy), Specilized classes, parameterized classes.

Dynamic Arrays, Associative Arrays, Array methods and usage, Tips for scoreboard Development

Need for Randomization, Controlling randomization, Constraints, Inline Constraints, Controlling constraints.

Need of Methodology, Constrained Random Verification, Verification Concepts

UVM Class Library, UVM Testbench, UVM Test, UVM Environment, UVM Scoreboard, UVM Agent, UVM Sequencer, UVM Sequence, UVM Driver, UVM Monitor

UVM Class Hierarchy, UVM Factory, UVM Config-db, UVM Callbacks, Parameterizing, Transactions, Phases, Event-pool, Field-macros, Messaging, Components vs Object

Basic TLM Communications, Communication Between Processes, UVM Analysis Communication

Data Item for Generation, Transaction Modelling, Driver Implementation, Sequencer, Monitor, Agent, Scoreboard, Environment, Test case, Top module

Configuration Database, Virtual Sequence and Virtual Sequencer, Advanced Score boarding Techniques – decl Macros, RAL Model

APB/AHB Slave IP Verification
Ethernet 1G MAC VIP Development

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Demo Videos

Video Reviews

Learner Reviews

I joined the Design Verification course to get knowledge of verification and job, I met my expectation, trainer was good, good Lab Instructor Support and the best part is 24/7 VPN Support, I experienced very good Lab Experience.

Madhukar Reddy

Awesome experience I had during learning my course. Management is too good they do for candidates at their extent placement is good. Everyone get chance. Happy to be the part of Samsung semiconductor through ChipEdge!

Dhyan Prakash

The course helped me to get industry kind of experience in the dv course. Excellent Trainer. 24/7 VPN access is excellent. The overall experience is fairly good. “Yes” Everything is fine. Training materiel and slides are good.

Sarika S


Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.


9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20  years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor-led online courses on weekends are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short/long). please check the “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Course Counsellors.

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

2 Weeks