Design For Testability (DFT) is a specialisation in the SOC design cycle, which facilitates a design for detecting manufacturing defects. With increase in size & complexity of chips, facilitated by advancement of manufacturing technologies, It has evolved as a specialization in itself over a period of time. DFT Engineers, works on introducing various test structures as part of the design flow, to increase the testability of logic, pads, memories, interconnects.
This course is designed for the working VLSI / Electronics engineers who want to learn / enhance their knowledge on Design For Testability (DFT) and become Skilled DFT engineers.
The course is designed and will be delivered by experts in DFT, as per current project requirements. Importance is given to cover the concepts, methodology thoroughly with good emphasis on hands-on training, using Industry Standard DFT tools with at least 50 % time allocated to lab sessions.
A winner is someone who recognizes his God given talents, works his tail off to develop them into skills and use these skills to accomplish his goals. – Larry Bird
At the end of this course, the candidate will be able to:
- Read in the netlist that has DFT logic inserted in it and along with the various SPF files in the ATPG EDA tool.
- Build the ATPG model.
- Run DRC checks on the design.
- Generate patterns for stuck-at and at-speed models.
- Review Test Coverage & do incremental ATPG.
- Write-out the patterns.
- Diagnose failure logs provided by the ATE engineer
Training Delivery Model:
- Weekends (Saturdays) : Instructor Lead classroom training
- Weekdays : Lab support through Email and WhatsApp
- Flexible learning with 24/7 Lab Access from home through VPN
- Lecture & Lab sessions go hand in hand, like corporate training
- Sessions will be interactive in nature
- Projects at end of the course
Who Can Attend This Course:
- Entry level / Experienced DFT engineers, who want to learn DFT in a systematic way from fundamentals to techniques, methodologies.
- RTL Design, Verification, Synthesis, STA and Physical Design Engineers, CAD Engineers who need to understand DFT for effective integration into their respective design flows.
- Application Engineers who need to understand DFT, for effective customer interactions & problem solving
- Faculty working in Engineering Colleges, teaching VLSI subjects.
- Anyone interested to learn basic to intermediate level of DFT concepts and tool flow.
- M.tech (VLSI) Interns/Freshers/Students
- Knowledge of digital design.
- Knowledge of ASIC / SOC design flow.
- At least 1 year of work experience in ASIC or SOC Design Flow.
- Prior knowledge of DFT is not required
Course Content outline:
Duration: 9 Weeks
Each module has associated labs. Theory session will be followed by hands on labs.
SCAN & JTAG Insertion
- Full ASIC flow – DFT
- DFT Basics
- Understanding of SCAN in depth
- Scan architecture overview
- Types of Scan
- Scan golden rules
- Understanding and analysis of DFT DRC
- Multiple clock handling
- DRC Fixing with examples
- Full scan insertion and stitching without compression
- Generate test protocol and understanding
- Basics/Need of Compression
- Compression techniques
- Scan insertion with compression
- On-chip clocking for at-speed testing
- Hierarchical Scan Design
- Top-Down Scan Insertion
- Boundary scan basics
- Boundary scan cell operation in detail
- JTAG basics, operation and state machine
ATPG & Simulations
- ASIC Flow
- DFT Overview
- DFT Flow
- Understanding of Defects and Faults
- Functional test Vs Structural Test
- Understanding of Silicon testing from Tester to gate level
- Fault Detection
- Faults and fault collapsing
- ATPG algorithm
- Fault models
- Types of fault models
- Different types of ATPG
- Stuckat fault model with an example
- Understanding of ATPG constraints
- Understanding of SPF
- ATPG DRC analysis [2-3 Live examples]
- ATPG for Stuckat fault model
- Test Coverage Vs Fault Coverage
- Usage of ATPG Graphical schematic viewer
- Analyzing feedback paths
- ATPG pattern simulation flow
- Stuckat pattern Simulation and failure debugging
- Analyzing ATPG faults
- Coverage improvement techniques
- ATPG pattern optimization
- At speed fault models
- Understanding Transition fault ATPG
- ATPG setup for transition fault model
- ATPG for Transition fault model
- Timing exceptions in atspeed testing
- Path delay fault modelling
- On-Chip clock controller
- Transition Pattern simulation
- Transition pattern Simulation failure debugging
- Introduction to Diagnosis
- Diagnosis Flow
- Analysing failure logs
Tools to be used:
- Industry Standard DFT Tool set will be used.
- Additional Lab Hours through VPN, to enable you spend more time on labs from home. This is on top of Trainer led lab sessions during sundays.
Assessment & Certification:
- Course completion certificate from ChipEdge.
- At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.
- 3 credit Course leading to M.S degree and Certification from Global University of Engineering, USA.
The trainer has 11+ years of VLSI industry Experience, with last 8 years exclusively in DFT and currently working as DFT lead for a services company. He has worked for customers like Texas Instruments, Intel.
He is passionate in teaching & sharing his knowledge and mentored entry / mid level engineers throughout his career.
I feel fortunate to have found one such unique course and enrolled for it. The course has given a lot of exposure to DFT and broken my idea that DFT is an easy job to do.
Trainer is very helpful even in very small and silly doubts explain everything asked to him. About course, it was very good. When I have started I have so many doubts but now at the end of this course doubts are clear with clear understanding of concepts.