Physical design interviews usually become technical very quickly.
One minute you’re talking about your project. The next minute someone asks why hold violations suddenly increased after CTS or what you’d check first if routing congestion appears even at moderate utilization.
That shift catches a lot of people off guard.
Most interviewers are not trying to hear textbook definitions word for word. They want to know whether you actually understand what happens inside a backend flow when something breaks. Because eventually, something always breaks.
And honestly, that’s normal in physical design.
What Interviewers Usually Want to See
Freshers often assume interviews are about memorizing commands or definitions. They’re not.
Interviewers care more about your reasoning.
If you explain why placement affects congestion or why skew changes after CTS, the discussion becomes much stronger immediately. Even if your wording isn’t perfect, showing real understanding matters more.
A candidate who understands tradeoffs generally performs better than someone giving memorized answers.
Floorplanning Questions
What is floorplanning? Why is it important?
Floorplanning is basically the starting point of physical implementation.
This is where macro locations, IO placement, power planning, and core dimensions get decided. A weak floorplan creates problems everywhere later — congestion, routing difficulty, timing failures, sometimes even power issues.
One thing students usually underestimate is how early decisions affect everything downstream.
A slightly bad macro placement can keep hurting the design all the way until signoff.
What affects macro placement?
Usually a combination of:
- Timing requirements
- Routing channels
- Power structure
- IO proximity
- Congestion risk
Macros that communicate heavily are generally placed closer together. Otherwise wirelength increases and timing becomes harder to close.
But in real projects, constraints often conflict with each other. That’s where engineering judgment comes in.
What is utilization in floorplanning?
Utilization refers to how much core area is occupied by cells and macros.
Higher utilization sounds efficient initially, but aggressive utilization creates routing congestion very quickly. Most designs stay within a safer range to leave room for buffers, CTS optimization, and routing resources.
Students often focus only on area reduction. Backend engineers usually think ahead about routability too.
Placement Questions
Difference between global placement and detail placement
Global placement spreads cells roughly across the chip while trying to reduce wirelength.
Detail placement comes later and legalizes the placement properly according to design rules.
You can think of global placement as rough organization and detail placement as cleanup plus optimization.
How does placement affect congestion?
Placement decisions directly influence routing demand.
If too many highly connected cells sit inside one area, routing resources get exhausted there. Congestion hotspots appear, and later stages become painful.
A lot of routing problems actually begin during placement, not routing itself.
That connection is important during interviews.
What is timing-driven placement?
Timing-driven placement prioritizes critical timing paths during optimization.
Cells on important paths get positioned more carefully to reduce delay. Without timing-driven optimization, placement may look clean physically but still fail timing badly.
Most modern high-performance designs rely heavily on timing-aware optimization throughout the flow.
CTS Questions
Why is CTS done after placement?
Because clock tree design depends on the physical locations of flip-flops.
Without placement information, the tool has no idea how to balance clock latency properly. If CTS happened before placement, the clock tree would become inaccurate once cells moved.
That’s usually the simplest way to explain it in interviews.
What is clock skew?
Clock skew is the difference in clock arrival times between flip-flops.
Too much skew creates setup or hold timing problems. Controlled skew can sometimes help timing closure, though.
That’s where useful skew comes into the discussion.
Useful skew vs harmful skew
Useful skew is intentionally introduced to improve timing on difficult paths.
Harmful skew happens unintentionally and creates violations instead of helping.
Interviewers ask this because they want to see whether you understand skew as an optimization parameter, not just a timing problem.
Routing Questions
Difference between global routing and detailed routing
Global routing estimates routing resources and identifies congestion regions early.
Detailed routing creates the actual wire paths and vias while following strict design rules.
Global routing is more predictive. Detailed routing is implementation-focused.
What causes routing congestion?
Usually some mix of:
- Dense placement
- Poor floorplanning
- Macro blockage
- Excessive connectivity in one region
Congestion rarely appears randomly. There’s almost always an upstream reason.
That’s something experienced interviewers like hearing.
What is antenna effect?
During fabrication, long metal wires can accumulate charge and damage gate oxides.
Antenna violations are fixed using techniques like antenna diodes, jumper insertion, or routing changes.
Most people memorize the definition. Fewer people explain why it matters physically.
STA Questions
What is static timing analysis?
STA checks timing paths mathematically without running dynamic simulation.
It analyzes whether signals can propagate correctly under different conditions and timing corners.
Without STA, validating large ASIC designs would become almost impossible practically.
Difference between setup and hold violations
Setup violation means data arrives too late.
Hold violation means data changes too early.
Freshers usually find hold fixing more confusing because the solution often involves intentionally adding delay rather than removing it.
That feels counterintuitive initially.
What are timing corners?
Different process, voltage, and temperature conditions affect circuit speed differently.
Designs must work reliably across all required corners, not just one ideal condition.
Slow corners usually stress setup timing. Fast corners expose hold issues more aggressively.
Physical Verification Questions
What is DRC?
DRC checks whether the layout follows manufacturing rules like spacing, width, and enclosure constraints.
Passing DRC means the layout is manufacturable geometrically.
What is LVS?
LVS compares the physical layout connectivity against the original schematic or netlist.
A clean LVS confirms the implemented layout matches the intended design electrically.
Questions That Usually Surprise Candidates
What if timing closes at block level but fails at top level?
This often points toward interface timing or top-level constraint issues.
Clock definitions, IO constraints, CDC paths, or integration-level timing assumptions become common suspects.
A lot of real debugging starts at integration boundaries.
What if routing fails even with reasonable utilization?
That usually suggests local congestion rather than overall utilization problems.
Congestion maps become important here because average utilization numbers sometimes hide severe hotspots.
What if hold violations appear after CTS?
Post-CTS hold violations are commonly caused by skew changes introduced by the clock tree.
The clock path behavior changes after CTS, which affects launch and capture timing relationships.
This is one of those issues students understand much better after seeing it happen in tools directly.
How to Prepare Properly
Reading physical design interview questions helps. But physical design becomes easier only after working through actual flows.
Running placement, analyzing timing reports, debugging congestion, fixing violations — that practical exposure changes how you answer technical questions.
Interviewers notice immediately when someone has worked with tools instead of only reading theory.
Even small project experience helps.
FAQ
What topics are asked in physical design interviews?
Floorpowrplan, placement, CTS, routing, STA, congestion, DRC, LVS, and timing closure are commonly discussed.
Are fresher interviews different from experienced-level interviews?
Yes. Freshers are usually tested on fundamentals and reasoning, while experienced engineers discuss real implementation challenges and project decisions.
Which tools are commonly expected?
ICC2, Innovus, PrimeTime, and basic Tcl scripting knowledge are commonly expected in backend interviews.
How important is STA knowledge?
Very important. Timing analysis questions appear in almost every physical design interview.
Is scripting necessary for backend roles?
Basic Tcl scripting is extremely common in physical design environments and helps automate flows and report analysis.
