What Every Physical Design Engineer Needs to Know About the VLSI Physical Design Flow
The gate-level netlist that arrives from the synthesis team is not a chip. It is a description of logic relationships between standard cells with no spatial information, physical wiring, or account of the parasitic effects that will ultimately determine whether the design meets its timing requirements.
Converting that netlist into a manufacturable chip is the job of the physical design engineer. It is a job that involves judgment at every stage, that produces consequences for every decision made, and that is evaluated ultimately by one criterion: does the final layout meet the design’s performance, power, and area targets in a form that the foundry can reliably fabricate.
This article walks through the physical design flow in VLSI from the point of netlist receipt through sign-off, explaining what each stage involves, what decisions it requires, and how those decisions affect the stages that follow.
Why Physical Design Is One of the Most Demanding Stages in the Entire VLSI Flow
Physical design is demanding in a way that is qualitatively different from the demands of other chip design stages.
The front-end stages of chip design are primarily abstract. RTL describes behavior. Simulation confirms behavioral correctness. Synthesis converts behavior into logic without physical geometry. In these stages, the design exists as text or logical connectivity without physical location.
Physical design introduces physical reality into the design for the first time. Cells must be placed in specific locations on silicon. Wires must be routed through specific metal layers following specific design rules. Timing must close not on estimated wire delays but on the actual parasitic resistance and capacitance of the physical wiring that the router has created.
This encounter with physical reality produces constraints that the front-end stages cannot fully anticipate. Wire lengths that the floorplan did not predict, routing congestion that placement created, clock distribution asymmetry that the design’s structural properties introduce. Physical design engineers navigate these constraints through a combination of tool proficiency, engineering judgment, and the iterative problem-solving that is the defining characteristic of the physical implementation process.
How Physical Design Engineers Receive Work from Front End Teams
The primary input that a physical design engineer receives from the front-end team is the synthesized gate-level netlist accompanied by the SDC timing constraint file that specifies the performance targets the physical implementation must meet.
The netlist is a structural description of the design in terms of standard cells from the target technology library, connected according to the logical connectivity of the RTL. It specifies which cells are present and how they are connected but says nothing about where they are located or how the connections between them are physically implemented.
The SDC file specifies the timing requirements that the physical implementation must satisfy. Clock definitions establish the frequency at which each clock domain operates. Input delay and output delay constraints establish the timing budget available for the logic between the chip’s boundary and its internal flip-flops. False path and multicycle path constraints identify timing relationships that should not be analyzed or that require more than one clock cycle to complete. Other key physical-design inputs can include LEF and technology files, Liberty libraries, macro abstracts, and related implementation data.
Physical design engineers review both the netlist and the timing constraints carefully before floorplanning, because the characteristics of the netlist and the constraints determine what the physical implementation will face at each subsequent stage.
What Floorplanning Decisions Define for Every Stage That Follows
Floorplanning is the stage where the physical design engineer makes the decisions with the greatest impact on the rest of the implementation.
Power Network Planning
The power network must distribute supply voltage from the chip’s pads/bumps or other power-delivery structures through a hierarchical structure of rings, straps, and rails to every standard cell in the design with IR drop low enough to maintain correct circuit operation.
Power network planning establishes how wide the power rings and straps will be, how dense the power grid will be in different regions of the chip, and where the pads/bumps or other power-delivery structures will be placed. These decisions are driven by the current density that different regions of the chip will draw during operation and the IR drop limits that the timing analysis must remain within.
A poorly planned power network creates IR drop violations in high-activity regions that cannot be resolved without revisiting the power network architecture after significant downstream work has been completed. Getting the power planning right during floorplanning avoids this expensive iteration.
Macro Orientation and Placement
Large macros, primarily memory arrays, must be placed before standard cell placement begins. The locations chosen for macros determine the placement area available for standard cells, the routing paths available for the connections between macros and the logic that accesses them, and the thermal distribution of the chip if the macros are power-intensive.
Macro placement decisions that place frequently communicating macros far apart create long timing paths between them that may be difficult to meet at timing closure. Decisions that cluster large macros in one region may create routing congestion in the area between the macros and the logic that accesses them.
IO Pad Placement
IO pad placement establishes where the chip’s input and output pads, plus pads/bumps or other power-delivery structures, sit in the I/O ring around the chip’s perimeter. The placement of signal pads affects the length of the connections between the pads and the internal logic they communicate with, which affects timing on paths that cross the chip boundary.
Power pad placement affects the resistance of the supply paths from the chip boundary to the internal power grid, which affects IR drop across the chip. IO pad placement decisions made during floorplanning define constraints that persist through the entire physical implementation and cannot be easily changed after routing has begun.
How Standard Cell Placement Affects Routing and Timing in Physical Design
Congestion Aware Placement
Standard cell placement that does not account for routing congestion creates regions where the routing tool cannot complete all connections within the available routing resources, resulting in either unrouted connections or significant detours that add parasitic delay to affected paths.
Congestion-aware placement distributes cell density across the placement area in a way that provides adequate routing resources in every region of the chip. Modern placement tools have congestion analysis capabilities that estimate routing demand during placement and adjust cell locations to reduce estimated congestion before routing begins.
Timing Driven Placement
Timing-driven placement optimizes cell locations to minimize delay on timing-critical paths. Cells that are connected by timing-critical nets should be placed close together to minimize the wire length, and therefore the parasitic delay, of those nets.
Modern placement tools implement timing-driven optimization as part of the core placement algorithm, using estimated wire delays based on the placement locations to guide the optimizer. Physical design engineers review the pre-route timing results after placement and identify paths where the placement has not achieved adequate timing margin, directing additional optimization effort toward those paths before routing begins.
What Clock Tree Synthesis Involves and Why It Is Critical to Physical Design Success
Clock tree synthesis builds the physical network of buffers and wires that distributes clock signals from their source to every sequential element in the design.
The objectives of clock tree synthesis include controlling clock skew and insertion delay while meeting transition/slew targets and managing power and area. Clock skew must be minimized because it directly reduces the effective timing window within which data must settle at each flip-flop.
A clock tree with high skew produces artificially tight timing margins on paths that connect flip-flops with large skew differences. These artificially tight margins may require timing closure work that would not be necessary with a well-designed clock tree. The quality of the clock tree is therefore a significant determinant of how much timing closure work the physical design team faces after routing.
Physical design engineers configure the clock tree synthesis tool with target skew, insertion delay, transition/slew, power, and area requirements for each clock domain, review the clock tree quality metrics, and iterate before routing.
How Routing Complexity Grows with Design Size and How Engineers Handle It
Large designs can require multiple metal layers, depending on the technology, with layers used for global routing, intermediate connections, and local cell connections. The routing tool must find paths for every connection while satisfying the design rules of the relevant layers.
Physical design engineers handle routing complexity primarily through the quality of the upstream work. Good floorplanning that provides adequate routing resources in every region, good placement that minimizes the lengths of critical connections and maintains manageable density, and good clock tree implementation that does not consume disproportionate routing resources all contribute to routing completing with fewer iterations and less congestion.
After routing, physical design engineers review routing results, then proceed through parasitic extraction, IR/EM analysis, sign-off STA, and physical verification before GDS/OASIS generation.
What Timing Closure Requires from Physical Design Engineers in Real Projects
Timing closure is the iterative process of resolving the timing violations that static timing analysis reveals after routing has been completed and accurate parasitic data has been extracted and back-annotated.
The violations that appear after routing are often more numerous and more severe than the pre-route timing analysis predicted, because the actual wire parasitics are higher than the estimates used during placement optimization. Physical design engineers must analyze these violations, identify the sources of each category of violation, and apply the appropriate optimizations to resolve them.
Setup violations, which indicate that data does not arrive at a flip-flop early enough relative to the clock edge, are resolved by reducing path delay. Options include moving cells closer together to reduce wire length, upsizing cells to reduce logical delay, restructuring the routing to reduce capacitance on critical nets, or requesting RTL or synthesis changes that reduce the logical depth of the path.
Hold violations, which indicate that data arrives too early relative to the clock edge, can be addressed by increasing path delay. Buffer insertion is one common technique for paths with insufficient delay.
The challenge of timing closure is that resolving violations on one path can create new violations on adjacent paths that share routing resources or receive their clock from the same clock tree node. Physical design engineers navigate this iterative process through the combination of tool-directed optimization and manual intervention on the violations that automated optimization cannot resolve efficiently.
How Physical Verification Catches Issues That Simulation Cannot
Physical verification confirms that the completed layout meets the foundry’s requirements for manufacturing and that the layout correctly implements the logical netlist.
Design Rule Check verifies that every geometric shape in the layout meets the minimum width, minimum spacing, enclosure, and other requirements specified by the foundry’s process design rules. Violating these rules would result in a chip that cannot be reliably manufactured or that has compromised reliability in operation.
Layout Versus Schematic verifies that the layout correctly implements the netlist. Every connection in the netlist must correspond to a physical wire in the layout. No spurious connections may exist in the layout that are not in the netlist. Every transistor in the layout must correspond to a transistor in the netlist. LVS violations indicate that the implementation does not match the design, which would result in a chip that does not function as intended.
Electrical Rule Check identifies electrical or reliability issues defined by the applicable foundry and tool deck. Depending on the deck, checks can include electromigration-related limits, antenna rules, latch-up-related conditions, and other electrical concerns before tape-out.
Physical design engineers review DRC, LVS, and ERC results before tape-out. Some findings may have formally approved waivers, so sign-off requires resolving violations or obtaining the required approval for accepted exceptions.
What Tools Physical Design Engineers Use and How Proficiency Affects Career Growth
The tools at the center of the physical design flow in VLSI are Synopsys ICC2 for physical implementation and Synopsys PrimeTime for static timing analysis.
Synopsys ICC2 is a widely used physical implementation platform. It handles floorplanning, placement, clock tree synthesis, routing, and timing-driven optimization in an integrated environment. Proficiency with ICC2, meaning the ability to configure and execute each stage of the implementation flow, to interpret the results and identify issues, and to apply the optimizations that resolve those issues, is the core technical capability that physical design roles require.
Synopsys PrimeTime is a widely used static timing analysis platform for both in-flow timing analysis during physical implementation and final sign-off timing analysis before tape-out. Understanding how to run PrimeTime, how to interpret its timing reports, and how to diagnose the sources of timing violations from the information it provides is the analytical foundation of timing closure work.
Career growth in physical design is directly correlated with the depth and breadth of tool proficiency. Engineers who can execute every stage of the physical design flow independently and who can handle complex timing closure scenarios with confidence advance more rapidly than those whose proficiency is limited to specific stages. ChipEdge’s Physical Design program develops this end-to-end proficiency through licensed Synopsys ICC2 and PrimeTime access and project work that executes the complete flow on real design blocks.
How the Physical Design Flow Connects Back to Front End Decisions Made Earlier
The physical design flow does not start from a blank slate. It starts from the output of a front-end process whose decisions have already established constraints that the physical implementation must work within.
The RTL coding style that the design team used affects what the synthesis tool produces. RTL with excessively long combinational paths produces a netlist with critical paths that are difficult to implement within the timing budget. RTL with inefficient coding patterns produces a netlist that uses more area than necessary.
The synthesis constraints that the front-end team specified determine what the synthesis tool optimized for. Accurate constraints produce a netlist optimized for the actual implementation requirements. Incorrect constraints produce a netlist that may appear to meet timing in synthesis but requires significant rework during physical implementation to meet the real requirements.
The chip architecture that the design team defined establishes the fundamental physical organization of the chip. The size and quantity of embedded memories, the number and organization of clock domains, and the communication patterns between major functional blocks all determine what the physical design engineer is working with from the first step of floorplanning.
Understanding these front-end connections is what allows physical design engineers to collaborate effectively with RTL and synthesis teams, to flag front-end decisions that will create physical design challenges, and to make requests for front-end changes that are justified by physical design requirements rather than appearing arbitrary to teams who have not seen the physical implications. This cross-functional awareness is one of the capabilities that distinguishes senior physical design engineers from those whose expertise is limited to physical implementation execution.
