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Gain Comprehensive Expertise In Physical Design Techniques Through Our Industry-Aligned Certification Course

Learn Physical Design Certification Course Offline from Experts with 10+ yrs. of Industry Experience.

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Gain expertise in RTL design principles, linting techniques, and CDC verification for complex digital designs.

Start Date

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Duration

5 Months

Training Type

Offline Classes

Designed for

  • Fresh engineering graduates from BE / B. Tech and Students from 8th Semester can also enroll
  • M.Tech (VLSI/Embedded/Power Electronics) Freshers and students
  • BE/ B. Tech Students from 8th Semester can also enroll.
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Course Overview

VLSI Physical Design course, specially designed for fresh graduates to get comprehensive training to start a career in VLSI Industry as a Physical Design Engineer. The course covers the latest industry requirements and is covered by trainers experienced in Physical Design. The course begins with introduction to Linux, Fundamentals to CMOS and Digital Electronics, Digital design using Verilog.

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*No Cost EMI

More About The Course

Course Delivery Model

VLSI Tools & Lab

Who Can attend this Course

Payments

Placement Assistance

Admission Procedure

Course Delivery Model

  • 600+ hrs. interactive learning.
  • Instructor Led live offline classes
  • Assesment After the Every Module
  • Group mock interviews by industry experts to prepare you better.
  • Duration - 5 Months ( Monday to Friday )

VLSI Tools & Lab

Synopsis Tools

  • Digital Design with Verilog: VCS.
  • Synthesis – Design Compiler Topographical.
  • Static Timing Analysis(STA): Prime Time SI.
  • Physical Design: IC Compiler 2 (ICC2)..
  • RC Extraction: Star RC.
  • Physical Verification: IC Validator

Technology Libraries To be Used

  • 14nm Finfet Libraries

Who Can attend this course

  • Fresh engineering graduates in ECE/EEE/Instrumentation/ Telecom/CSE/ Mechatronics passed outs.
  • M.Tech (VLSI/Embedded/Power Electronics) Freshers and students.
  • BE/ B. Tech Students from 8th Semester can also enroll.

Payments

  • Pay through Debit card/ Credit card/ Net banking/ UPI.
  • Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months of EMI without paying any additional cost on interest.

Placement Assistance

  • Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
  • We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.

Admission procedure

Step 1: Online Admission Test

Take online test for 90 mins with 60 MCQs. Syllabus includes Aptitude, Digital Electronics, Electronic Devices.

Step 2: Seat Confirmation

Enroll in the course, if selected. Start your preparation by getting access to the pre-requisite materials.

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Why Choose ChipEdge

Online
VLSI Lab

Synopsys
Tools

Expert
Trainers

Placement
Assistance

State of the
Art LMS

Industry
Relevant Courses

Industry
Connect

Alumini
Network

Curriculum - Offline Physical Design Certification Course

  • Introduction to Linux,
  • Command Line Operators,
  • File Operations, Processes,
  • Text Editors,
  • Text Manipulating,
  • Network Operations,
  • Special Keystrokes
  • GVIM

  • Number System, Boolean Algebra,
  • SOP and POS, K-Map,
  • Combinational circuits, Sequential circuits,
  • Finite State machines,
  • Frequency Division,
  • Setup and Hold time checks,
  • Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations, FIFO Depth Calculation

  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics: Atomic Structure, Electronic Configuration, Doping, Diode - Biasing and VI Characteristics
  • MOSFET: Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second-order effects: Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology: Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion Implementation, Lithography

  • Introduction to Verilog
  • Applications of Verilog HDL
  • Verilog HDL language concepts
  • Verilog language basics and constructs
  • Data Types, Nets and registers, Arrays
  • Verilog Operators : Logical operators, Bitwise and Reduction operators, Concatenation and conditional operators, Relational and arithmetic, Shift and Equality operators, Operators precedence.
  • Type of assignments: Continuous assignments, Inter/Intra assignments, Blocking and Non Blocking assignments, Execution branching,Tasks and Functions
  • Finite State Machine (FSM) : Basic FSM structure, Moore Vs Mealy, Common FSM coding styles, Registered output.

  • ASIC Design flow and role of Synthesis
  • Synthesis flow
  • writing timing constraints in SDC format
  • Constraining the design for timing, power, area goals, set optimization techniques.
  • Synthesize the design.
  • enerate and analyze the reports, save the netlist and SDC.

  • Formal Verification
  • Understanding & Matching compare points
  • Debugging non equivalent points
  • What-If Analysis

  • Features of TCL and Applications.
  • TCL commands, Variables, arithmetic expressions, comments, identifiers, reserved words, data types, decisions, loops, arrays, strings, file I/O and procedures.
  • Scripting exercises from simple problems to complex problems, in an incremental manner and using tools like Prime Time, ICC2.

  • Introduction to physical design and Physical Design Flow, Data preparation : Files required for PD ( Netlist, SDC, Libraries, Technology files, TLU+), the contents of each input file.

  • Sanity Check
  • Goals of Floorplanning
  • Different aspects of floor planning
  • Rectangle/Rectilinear floor plans
  • Die size estimation (Core Utilization, Aspect ratio)
  • IO placement
  • Macro placement and guidelines
  • Channel-width estimation

  • Goals of Power Routing
  • Power distribution structure (Rings, straps and follow-pin/std cell rail)
  • Metal stack information
  • Power planning methodology
  • IR drop analysis, types of power consumption
  • Why Low power and low power techniques. Electro-migration analysis

  • Goals of Placement, types of placements
  • Pre-place (End-cap, Tap & I/O Buffer) cells
  • Placement optimization
  • Congestion analysis
  • Timing analysis
  • Tie-cells
  • High-Fanout Net Synthesis
  • Scan chain re-order
  • Path Grouping and creating Bounds

  • STA Overview and concepts
  • Basic timing checks (setup, hold)
  • Understanding timing constraints (SDC)
  • Timing corners
  • Timing report analysis
  • General optimization techniques
  • Typical causes for timing violations and strategies for fixing the same
  • Pre-CTS optimization to Fix setup violations.

  • Goals of CTS, Types of Clock-tree
  • Constraints for CTS
  • Building clock tree
  • Analyze the results
  • Post-CTS optimization : Fixing Setup and Hold violations.

  • Goals of Routing
  • Stages of Routing: Global Routing, Track assignment and Detail Routing
  • Routing options
  • Fixing of routing violations (DRC, LVS)
  • Post route optimization
  • Issues in routing and guidelines for optimum routing results.

  • Post layout STA using SPEF
  • Multi Mode Multi Corner STA
  • Derating factors
  • PVT, OCV Variations
  • Crosstalk Analysis

  • What is ECO
  • Types of ECO
  • Timing & Functional ECO
  • Performing the ECO placement and routing.

  • Physical Verification (DRC, LVS),
  • IR drop analysis,
  • Electro-Migration Analysis

  • Projects will be given converging Netlist to GDSII flow. Various projects that will allow the students to understand the intricacies of implementation for minimum area, low power, high performance. The method of execution will be similar to typical block level Physical Design work/project in the industry. Block level input database will be given and the participant has to deliver GDS II, after cleaning all the issues during sign-off checks.
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What Our Learners Have to Say

I had completed my BE and I was looking for a career change. Since I had no idea about this field, whatever concepts I was learning here were new to me. Trainer support here was very good as he had a great patience and was ... Read More

- Rakshith M A

I have done a Physical design course from ChipEdge. It is the best platform for anyone to start their career in the VLSI domain. The trainer's interact with each learner in a very friendly way. We also had industry level expert sessions every ... Read More

- Bharath Yadav

I have joined a physical design course in 2020. I have to say teaching is good and lab access via VPN is 24*7 available. They provided a seamless experience all the way through ... Read More

- Leela krishna Namburi

FAQ

We provide placement assistance by arranging interview opportunities with hiring companies. This is complimentary service from ChipEdge, without charging any extra amount for this. We charge only for our training, but not for placements.

We provide placement support until candidate gets job. To Ensure Successful Placements, We provide added support including mentorship, fundamentals classes, soft skills training, mock interviews Etc.

Salary Range For Freshers Is From 3- 4 Lakhs Per Annum In Service Companies. Salaries In Product/MNC Companies Can Range Between 7 To 16 Lakhs.

Though 3-4 LPA appears similar to software salaries, your real growth comes after 3 years. First 2-3 years are to be considered as career building phase, to learn as much as you can and do not compare with others / IT salaries.   Your knowledge will be your power and your career / salary growth from 4th year onwards depends on your talent/knowledge.

Each year many companies visit ChipEdge for recruiting the various entry level positions because of the quality training that we offer. 

For complete list of companies visit https://ChipEdge.com/view-hiring-companies/

We use 28nm,14nm libraries for labs, projects.

We use the latest and genuine versions of Synopsys Tools for our courses. please check course pages, for the list of tools used for that respective course. We provide a dedicated tool license for every learner during the lab/project work.

This is the biggest advantage with ChipEdge courses, as quality and standard EDA/VLSI tools are important for any VLSI course. And these tools are typically very costly ranging from $50,000 to $200,000 per license per year. Many service companies cannot afford these tools. Thanks to the EDA/Tool companies for giving these tools at subsidized & affordable rates to training companies, so that engineers can get trained on these tools.

We do have installment options for some courses. EMI option is available through our partner organizations, who provide loans for training programs. Please check with our learning advisors.

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