VLSI Physical Design Flow is a cardinal process of converting synthesized netlist, design curtailment and standard library to a layout as per the design rules provided by the foundry. This layout is further sent to the foundry for the creation of the chip.
Very Large Scale Integration (VLSI) Design Flow is an algorithm with definite objectives some of them consist of wire length, minimum area, and power optimization. Fundamentally VLSI starts from where Design Flow ends.
Steps in VLSI Physical design Flow are divided into several main processes because of its tremendous complexity. The very first step of partitioning divides a circuit into smaller sub-circuits or modules, each of which can be constructed and examined separately. Floorplanning determines the dimensions of all the blocks and places them in appropriate spots on the chip. Another step is power planning, which distributes power (VDD) and ground (GND) nets throughout the chip, and is commonly associated with floorplanning. Placement is the process of determining the geographic placements of all cells within a block. Clock network synthesis establishes how the clock signal is buffered, gated and routed to fulfil specified skew and latency criteria. The next step would be global routing which allocates routing resources that are used for connections. Within the global routing resources, detailed routing assigns routes to individual metal layers and routing tracks. Lastly, timing closure is used for unique placement or routing strategies to improve circuit performance.
The Following are the Main Steps in VLSI Physical Design Flow:
Create a gate-level netlist (after synthesis)
The netlist is the result of the synthesis process and is the foundation for physical design. Synthesis translates RTL designs written in VHDL or Verilog HDL into gate-level specifications that can be understood by the next set of tools. The cells employed, their interconnections, the area used, and other parameters are all listed in this netlist.
The next step of partitioning helps in dividing the chip into separate chunks. This procedure is performed primarily to distinguish between distinct functional blocks and to facilitate placement and routing. When the design engineer separates the overall design into sub-blocks and then proceeds to design each module during the RTL design phase, this is known as partitioning.
Under this step, we calculate the dimensions of all the blocks and place them in appropriate spots on the chip. This step is performed to keep the blocks that are highly connected close to one another.
Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing. Every PnR tool provides various commands/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray to place and optimize it for better QoR. Placement does not place only the standard cells present in the synthesized netlist but also places many physical only cells and adds buffers/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps which the tool performs during the placement and optimization stage.
Static Time Analysis
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
Another way to perform timing analysis is to use dynamic simulation, which determines the full behaviour of the circuit for a given set of input stimulus vectors. Compared to dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit. STA is also more thorough because it checks all timing paths, not just the logical conditions that are sensitized by a set of test vectors. However, STA can only check the timing, not the functionality, of a circuit design.
Clock Tree Synthesis (CTS)
Clock Tree Synthesis(CTS) is one of the crucial steps in VLSI physical design flow. It is used to reduce skew and insertion delay. This step helps distribute the clock evenly among all sequential elements of a design.
Routing helps in making the links between the cells and the blocks. There are two types of routing: global routing and detailed routing. Connections are routed through global routing, which assigns routing resources. It also keeps track of a network’s assignment. Whereas, the actual connections are made by detailed routing.
Physical verification ensures that the produced layout design is valid. This involves ensuring that the layout is correct and includes all technological prerequisites, density verification, cleaning density etc.
VLSI Physical Design Flow is a complicated specialisation that has grown in popularity over the last two decades. VLSI engineers have a promising future because they are required to design chips or integrated circuits that are used in nearly every device you use today. With Chipedge’s course on VLSI 16 week physical design course you could learn all about physical design flow. Chipedge is the best VLSI training institute that offers best VLSI courses. Look out for VLSI training calendar for more information on courses. This VLSI training institute offers various online VLSI courses. There are various courses that are being offered by them like Physical Design course, Design Verification course, ASIC verification course, RTL Design Course and many more. Enroll yourself today for the Online VLSI Courses.