Introduction
Every VLSI aspirant has that one interview moment, the pause after a question, the rush to recall concepts, the uncertainty of whether the answer is right. More often than not, it comes down to how well you’ve prepared key physical design interview questions. This blog is designed to change that moment for you. Instead of hesitation, you’ll build clarity. Instead of guessing, you’ll respond with confidence. Because the right preparation doesn’t just help, it transforms how you perform.
Here are the top 20 physical design interview questions that frequently come up during campus recruitment drives, along with insights into what interviewers really look for.
Advanced Library & Timing Concepts
1. What is a ‘Library Characterization’ and why is it needed?
Logic gates don’t have fixed delays. Characterization (.lib generation) defines how a cell behaves under different input transition times and output loads.
2. What is ‘OCV’ (On-Chip Variation)?
It accounts for local variations in PVT (Process, Voltage, Temperature) across the same chip. We apply “derates” to make timing analysis more pessimistic.
3. Explain the ‘Recovery’ and ‘Removal’ checks.
These are timing checks for asynchronous signals (like Reset). Recovery is like Setup; Removal is like Hold.
4. What are ‘Multi-Vt’ cells and how are they used in PD?
Cells with different Threshold Voltages (Vt).
LVT (Low Vt): Fast but high leakage. Used for timing-critical paths.
HVT (High Vt): Slow but low leakage. Used to save power on non-critical paths.
5. What is ‘Max Transition’ and ‘Max Capacitance’ violation?
These are “Design Rule Constraints” (DRV). If a signal takes too long to switch (Transition) or drives too much load (Cap), it can lead to timing failure or reliability issues.
Floorplanning & Macros
6. What is a ‘Halo’ and how does it differ from a ‘Blockage’?
A Halo is a keep-out region attached to a macro that moves with it. A Blockage is a fixed area on the floorplan where no cells can be placed.
7. What is ‘Abutment’ in floorplanning?
Placing two macros side-by-side so they share a power/ground boundary or directly connect without long routing.
8. Why do we place ‘Decap Cells’ in the design?
Decoupling capacitors act as local charge reservoirs to prevent “IR Drop” (voltage sag) during high-speed switching.
9. Explain the ‘Flyline’ analysis.
A visual representation of the logical connections between macros and standard cells used during floorplanning to minimize wire length.
Placement & Optimization
10. What are ‘Filler Cells’ and when are they added?
Added at the very end of placement to ensure continuity in the N-well and power rails and to satisfy density rules.
11. What is ‘Spare Cell’ insertion?
Functional cells (NAND, NOR, etc.) that are floating in the layout. They are used for “Metal-only ECOs” to fix logic bugs after the silicon is manufactured.
13. What is ‘High Fan-out Net’ (HFN) synthesis?
Handling signals like Reset or Enable that drive thousands of pins by building a buffer tree (similar to CTS but for data signals).
Clock Tree Synthesis (CTS)
14. What is ‘Clock Gating‘ and how does it impact CTS?
It saves power by shutting off the clock to inactive blocks. In CTS, the “Integrated Clock Gating” (ICG) cell becomes a sink that must be balanced.
15. What is ‘NDR’ (Non-Default Routing) and where is it used?
Using wider wires or double spacing for clock signals to reduce resistance and protect against crosstalk.
16. Explain ‘Clock Jitter’.
The short-term variation of a clock’s edge from its ideal position. It is modeled as a “Uncertainty” in STA.
Routing & Signal Integrity
17. What are ‘Via Pillars’ (or Via Stacks)?
Using multiple vias between layers to reduce resistance and improve electromigration (EM) performance.
18. What is the ‘Electromigration’ (EM) problem?
The physical displacement of metal atoms due to high current density, which eventually leads to an open circuit (wire break).
19. Explain ‘Double Patterning’ in 7nm and below.
When features are too small for a single lithographic mask, the layout is split into two masks (Coloring) to be manufactured in two steps.
Physical Verification
20. What is ‘ERC’ (Electrical Rule Check)?
Checks for electrical violations like floating inputs, short circuits between different power domains, or well-tap density.
21. What is ‘Density Violation’ and how is ‘Metal Fill’ used to fix it?
Foundries require a minimum percentage of metal on each layer for chemical-mechanical polishing (CMP). “Metal Fill” adds dummy metal shapes to meet these targets.
Conclusion
At some point, preparation stops feeling like effort and starts feeling like confidence. That’s what happens when you spend time with the right physical design interview questions. You begin to recognize patterns, structure your answers better, and think more clearly under pressure. With the right guidance and industry-focused training from ChipEdge, this process becomes more effective and goal-driven. Keep practicing, stay consistent, and trust your progress, the results will show when it matters most.
