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Industry-Validated Training to Strengthen Your VLSI andASIC Verification Skills

Learn Design Verification Course Online from Experts with 10+ yrs. of Industry Experience.

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The course is Designed & delivered by Verification Experts from the VLSI Industry,with Live Online Classes on Weekends.

Start Date

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Duration

5 Months

Training Type

Live Online Classes

Designed for

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar
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Course Overview

Design Verification (DV) is also called RTL / Functional Verification, which involves testing the Design for Functionality. ASIC Verification in VLSI is similar to testing work in the software industry. In any VLSI Project, the number of Design Verification Engineers is more than other skill sets. Hence a number of job opportunities is more for Verification Engineers. Trained DV Engineers are on demand most of the time.

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*No Cost EMI

More About The Course

Course Delivery Model

Duration & Timing

VLSI Tools & Lab

Who Can attend this Course

Payments

Placement Assistance

Course Delivery Model

  • Live Online training
  • Module-specific Lecture sessions & Labs conducted hand-in-hand.
  • Emphasis on Lab driven hands-on training aimed at building key skills.
  • Group mock interview sessions conducted by Industry Experts.
  • Weekdays: Doubt clarification support through WhatsApp.
  • Flexible learning with Lab Access from home through VPN.

Duration & Timing

More than 400Hrs of Interactive Learning

  • 5 months - Design Verification Course (Weekends)
  • 3 Hours - Live lecture sessions Every Weekend.
  • 3 Hours - Live Online Lab Sessions Every Weekend.
  • Weekdays Doubt Clarification Support.

VLSI Tools & Lab

Synopsis Tools

  • VCS Tool Suite.

Technology Libraries To be Used

  • 14nm Finfet Libraries

Lab Access

  • Flexible learning running on high-end cloud servers
  • Access VLSI Lab anytime anywhere using VPN

Who Can attend this course

  • Working Professionals (including interns..) from the VLSI / Embedded industry who are currently working in areas like RTL Design, FPGA Design, Board Level Testing and would like to upskill on SV, UVM either to perform better in current role or switch your role / career to ASIC Design Verification
  • Professionals from IT / Electronics / Any other sector interested in switching to VLSI industry for career growth.
  • Faculty working in Engineering colleges interested to switch to VLSI industry.

Qualification

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar

Payments

  • Pay through Debit card/ Credit card/ Net banking/ UPI.
  • Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months of EMI without paying any additional cost on interest.

Placement Assistance

  • Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
  • We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.
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Why Choose ChipEdge

Online
VLSI Lab

Synopsys
Tools

Expert
Trainers

Placement
Assistance

State of the
Art LMS

Industry
Relevant Courses

Industry
Connect

Alumini
Network

Curriculum - Online Design Verification Course

  • Introduction to Linux,
  • Command Line Operators,
  • File Operations, Processes,
  • Text Editors,
  • Text Manipulating,
  • Network Operations,
  • Special Keystrokes
  • GVIM

  • Number System, Boolean Algebra,
  • SOP and POS, K-Map,
  • Combinational circuits, Sequential circuits,
  • Finite State machines,
  • Frequency Division,
  • Setup and Hold time checks,
  • Advance Design Issues: Metastability, Noise Margins Power, Fanout, Timing Considerations, FIFO Depth Calculation

  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode - Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion Implementation, Lithography

  • Introduction to Verilog
  • Overview of Digital design with Verilog HDL
  • Hierarchical Modeling Concepts: Top-down, bottom-up Design Methodology, modules, components of simulation, stimulus block.
  • Modeling Styles in Verilog: Behavioral or algorithmic level, data flow level, gate level, switch level.
  • Basic concepts: Lexical conventions, Operators, data types, System tasks, directives, File Input and output.
  • Modules and Ports: Module definition, port declaration, connecting ports, hierarchical referencing.
  • Behavioral Modeling: Initial and always, blocking and non blocking statements, delay control, event control, conditional statements, loops, sequential and parallel blocks.

  • Verification Concepts:
  • ✓ ASIC Design Flow
  • ✓ Verification Flow
  • ✓ Test bench Architecture
  • ✓ Verification Plan
  • Verification of combinational and sequential circuits:
  • ✓ Examples: Half adder, full adder, Encoder, comparator and their verification
  • ✓ Sequential circuits Verification: - D-FF, Shift registers
  • ✓ Parameters and parameterized modules
  • ✓ o Mini project using Verilog

  • Introduction to System Verilog - Basic Data types, Enum, Packages
  • Arrays Packed and Unpacked and Queues
  • Dynamic and associative Arrays and their methods
  • Interfaces, Modports, Programming Blocks, Clocking Blocks, Procedural Blocks
  • Creating Instances, Connecting DUT and TB via Interfaces
  • Tasks and Functions
  • Threads, Fork Join, Fork join_none, Fork join_any
  • Virtual interfaces
  • Semaphore
  • Mailbox
  • OOPs Concepts - Classes, objects and handles, Polymorphism and Inheritance
  • Virtual Methods, Static Variable and Methods
  • Shallow copy, Deep Copy
  • Parameterized classes, Abstract Classes

  • Randomization and Constraints
  • Coverage Based Verification: Cover points and bins, cross coverage
  • Assertions
  • DPI Calls

  • Motivation for UVM
  • Evolution of UVM
  • Components in UVM Testbench
  • Creating Test Stimulus
  • Phasing in UVM

  • Introduction to TLM
  • Ports, exports, implementation
  • Analysis ports
  • TLM FIFO
  • Analysis FIFO
  • Request-response channel
  • Sequencer - driver interaction
  • Sockets and transport channels

  • Factory Overrides: by instance, by type
  • UVM Resource : Config db and resource db
  • Sequence

  • Agent,
  • Env,
  • Test,
  • Scoreboard,
  • Monitor,
  • Coverage

  • Data Item for generation
  • Transaction Modelling
  • Driver implementation
  • Sequencer
  • Monitor
  • Agent
  • Scoreboard
  • Environment
  • Testcase
  • Top Module

  • RAL Model,
  • Integration with DUT,
  • UVM Tips & Tricks
  • Virtual Sequence

Advanced Peripheral Bus (APB) Protocol training involves Protocol theory, concepts read and write timing cycles, and operation states. Advanced concepts on error response of APB will also be covered. Component development of APB Slave, and Verification of APB Slave in UVM environment.

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What Our Learners Have to Say

I have attended a VLSI Design Verification course. Initially I was not much aware of the VLSI domain. ChipEdge provided me a great platform for learning VLSI. They provided VCS Synopsys tool access 24*7 through VPN. ... Read More

- Rabi Ahir

I have done a Design Verification course in Chipede. Training was excellent with good interaction. Recording facility is excellent for revision. Course was practically informative. The way of explaining is good. The course helped me to ... Read More

- Hemanth Kumar

I have completed Design Verification from ChipEdge. I got to know about this institute through my friends. ChipEdge is the Best platform to start our career in the vlsi domain. ... Read More

- Maneesha Murali

FAQ

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Session Break

11.30 am to 01.00 pm – Lab Session

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

ChipEdge trainers are typically having 10 to 20 years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab” tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs. please check with our Course Counsellors.

ChipEdge provides placement help to all candidates by providing them industry interview opportunities.

After a successful course completion, certificates will be provided.

2 weeks

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