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Certificate Course in RTL Design

Learn RTL Design Course Online from Experts with 10+ yrs. of Industry Experience.

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Gain expertise in RTL design principles, linting techniques, and CDC verification for complex digital designs.

Start Date

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Duration

5 Months

Training Type

Live Online Classes

Designed for

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar
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Course Overview

RTL design is an essential step in the development of digital designs, where the functionality of a circuit is described using a hardware description language.

Lint and CDC analysis are crucial verification techniques to ensure the RTL design is free from potential issues and to handle clock crossing scenarios.

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*No Cost EMI

More About The Course

Course Delivery Model

Duration & Timing

VLSI Tools & Lab

Who Can attend this Course

Payments

Placement Assistance

Course Delivery Model

  • Live Interactive Online Sessions on Weekends
  • 3 hours - Live lecture sessions every weekend.
  • 3 Hours - Live Online Lab Sessions Every Weekend.
  • Module specific Lecture sessions and Labs conducted hand-in-hand.
  • Emphasis on hands-on lab sessions aimed at building key skills.
  • Weekdays: Lab support through WhatsApp.
  • Flexible learning with Lab Access from anywhere, any time.

Duration & Timing

  • 20 weeks / 5 months
  • Total 120 Hours of Instructor Led Live Sessions
  • 40 Hours of Self Paced Learning for foundation modules
  • 6-8 Hours/ week Commitment is required for better Learning outcome

VLSI Tools & Lab

Synopsis Tools

  • VCS — For Simulations and Debugging.
  • Spy Glass

Lab Access

  • Flexible learning with online 24x7 lab access running on high-end cloud servers
  • Access VLSI Lab anytime anywhere using VPN

Who Can attend this course

  • Working Professionals (including interns) from the VLSI / Embedded industry who want to upskill on ASIC design methodologies, microarchitecture design, RTL coding in their current role or switch your role / career to RTL Design.
  • Professionals from IT / Electronics / Any other sector interested in switching to VLSI industry for career growth.
  • Faculty working in engineering colleges are interested in switching to the VLSI industry.
  • Students and Freshers who want to start their career in semiconductor industry

Qualification

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar

Payments

  • Pay through Debit card/ Credit card/ Net banking/ UPI.
  • Avail no cost EMI option with ZERO processing charge from our financial partners. You can choose 6 to 9 months of EMI without paying any additional cost on interest.

Placement Assistance

  • Our Placement Desk works closely with the leading VLSI companies to meet their entry level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The Hiring companies include both MNC and Service Companies.
  • We provide placement support as a complimentary service until the candidate gets the job. Interested candidates need to register with the placement desk for further assistance. For more information, please speak to our Learning Advisor.
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Why Choose ChipEdge

Online
VLSI Lab

Synopsys
Tools

Expert
Trainers

Placement
Assistance

State of the
Art LMS

Industry
Relevant Courses

Industry
Connect

Alumini
Network

Curriculum - Online RTL Design

  • Introduction to Linux,
  • Command Line Operators,
  • File Operations, Processes,
  • Text Editors,
  • Text Manipulating,
  • Network Operations,
  • Special Keystrokes
  • GVIM

  • Number System, Boolean Algebra,
  • SOP and POS, K-Map,
  • Combinational circuits, Sequential circuits,
  • Finite State machines,
  • Frequency Division,
  • Setup and Hold time checks,
  • Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations, FIFO Depth Calculation

  • Electronic Devices, Power Sources, Thevenin and Norton Theorem
  • Semiconductors Device Physics : Atomic Structure, Electronic Configuration, Doping, Diode - Biasing and VI Characteristics
  • MOSFET : Regions of operation, VI Characteristics
  • Function implementation using CMOS
  • Stick Diagram and Layout
  • Second order effects : Body Effect, Channel length modulation, Punch through, subthreshold conduction, DIBL
  • Process Technology : Clean Room, Wafer manufacturing, Oxidation, Diffusion, Ion Implementation, Lithography

  • ASIC Flow, Module, declaration and  Instantiation, Components of simulation,  Procedural blocks, Lexical conventions.
  • Data types, Module Parameters, Operators, Primitives, Functional representation in Verilog.
  • Arrays, Memories, System tasks, compiler  Directives, Continuous and Procedural.
  • Assignments, Examples of Blocking and Non blocking statement.
  • Race Condition, Timing Controls Sequential  and Parallel Blocks, Conditional Statements,  loops Statements.
  • Task, Functions, Difference between task and  Function.

  • ASIC Design Flow from Specifications to GDS II (frontend and backend process )
  • Verilog Synthesizable accepts to develop RTL Code for given functionality 
  • Synthesis guidelines for combinational logic  coding 
    1.Procedural block and continuous  assignment,
    2. Mux Logic, Mux logic with/without priority coding,
    3. Incomplete sensitivity list,
    4. Unintended latch,
    5. Functions vs always procedural blocks
  • Synthesis guidelines for sequential logic  coding 
    1. Coding sequential flipflop 
    2. Coding 1-bit FF with Synchronous reset  and Asynchronous reset 
    3. Coding 1-bit FF with condition and  combinational logic
    4. Coding series 1-bit, 3-bit FF
    5. Coding 1-bit latch
  • Synthesis guidelines for combinational logic  coding  
    1. State encoding 
    2. Present state storage assignment 
    3. Next state combinational logic 
    4. Outputs: Possible combination
    5. State encoding-one Hot

  • Clocks and Resets: Concept of Clock,  Synchronous Signals, Asynchronous Signals, Clock Domain, SynchronousDesign.
  • Meta-Stability: Sampling STABLE value and  Changing value on CLOCK,Impact of Metastability, Metastability and Storage  element, Examples of Metastable conditions.
  • Synchronous Methods and Multi-clock  domain: Asynchronous input, Synchronizing the Asynchronous input, Synchronizing the  Asynchronous reset, Multi-Clock Domain  design, Synchronizing the clock domains.
  • Micro Architecture Implementation: What is  Micro Architecture? Thinking Micro  Architecture, Example of Micro Architecture  Implementation.

  • Partition for Design Reuse
  • Keep related Combinational logic together.
  • Register Block outputs
  • Partitioning by Design Goal
  • Keep Sharable resources together
  • Isolate special functions
  • Write technology independent code
  • Isolate technology dependent code

  • How Lint Works
  • Lint Goals & Tools.
  • Lab -Spyglass Explorer, Lint Violations & Analysis
  • Spyglass tool flow – RDC
  • Spyglass Design setup
  • Goals Setup & Analyze Results
  • Common Scenarios & Waivers

  • Clock domain Crossing (CDC) Goals
  • Reset Checks, Violation Analysis & Debugging
  • Reset Check Qualifiers
  • Clock Reset Rules
  • CDC Goals Setup
  • CDC Goals & Constraints
  • Block Box Handling
  • CDC Violations & Debugging
  • CDC Setup Port Coverage
  • CDC Structural Verification

  • Synthesis overview & Flow
  • Synthesis Flow using Design Compiler
  • Understanding technology library
  • HDL coding guidelines for Synthesis
  • Timing Checks
  • Constraining design
  • Compiling/Optimizing Design
  • Reporting and Analyzing QoR

  • Low Power Synthesis Need ?
    Low Power Methods
    Low Power cells
  • Formality – Equivalence checking
  • Scan Insertion

  • STA overview.
  • STA engine & design inputs.
  • Handling complex clocking
  • Timing Exceptions
  • Post Layout STA flow
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What Our Learners Have to Say

Everyone Will Know Something More Valuable About Education After Completing Any Type of Course in Chipedge. The Way they will Train us is excellent. The trainers train us in a well understanding manner. ... Read More

- Sonti Satish Goud

Best institute for vlsi physical design course. Very good lab assistance and placement opportunities. LMS procedural learning helps to understand concepts easily. Trainers are Working professionals who coach for the candidates. ... Read More

- Shashi Kumar

FAQ

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions, you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Session Break

11.30 am to 01.00 pm – Lab Session

The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20 years of VLSI industry experience and currently working in latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences  is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by majority of product / MNC companies in semiconductor(VLSI) industry world wide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short / long). please check “Lab” tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provides loans for training programs. please check with our Course Counsellors.

Chipedge provides placement help to all candidates by providing them industry interview opportunities.

After a successful course completion, certificates will be provided.

2 weeks

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