The Key Techniques Used in Design for Testability

Mittu George
July 15, 2024
10:24 am
1827

The Key Techniques Used in Design for Testability

Mittu George
July 15, 2024
10:24 am
1827

Without a way to easily check if everything works during the design process, finding problems later can be a nightmare. That’s where Design for Testability (DFT) comes in. DFT helps ensure circuits work correctly from the beginning, saving time, and money in the long run. It is like a cheat code used in the design process to make testing easier. Read along to learn more about the techniques used in DFT to achieve a smooth and efficient testing process.

What is Design for Testability?

Design for testability is the process used in the development stage of a system to make it easier to test for defects. Its emphasis on building hardware or software systems with testing in mind has made it an important practice in the chip production industry. It gives better control of the system by allowing it to set specific conditions within different parts of the system and improves observability with the ability to monitor the state of the internal components at all times. A VLSI course in DFT can teach you the fundamentals needed to capitalize on these benefits.

Techniques in DFT

There’s no single technique that could be used in all cases. So, one has to be carefully chosen to fit the purposes of the design under inspection. The techniques used in DFT are broadly divided into two categories: Ad-hoc and Structured.

Ad-Hoc Techniques:

Good design practices that are known to work well through experience are the guidelines for ad-hoc DFT. Some of its key aspects are:

Modular design

One of the important steps in designing a testable chip is partitioning the system into smaller and distinct modules such that there is an effective DFT technique to test each one of them. This improves the observability and controllability of each section.

Test points

Strategically placed test access points are inserted within the design for target testing. These test points can be Control Points (CPs) and Observation Points (OPs) and some points which are both.

Structured Techniques

Structured techniques involve adding special tools and features to your circuit specifically for testing purposes. Unlike ad-hoc techniques that rely on good design practices, these incorporate dedicated circuitry to make testing more efficient and thorough. Some common structured DFT techniques include:

Scan path testing

Scan path testing builds upon the full scan design by adding circuitry that allows you to shift test patterns. This lets you quickly load all the flip-flops with test data and then examine their outputs for verification, streamlining the testing process.

Boundary Scan

The IEEE 1149.1 standard defines a protocol for testing the connections between different chips (ICs) on a circuit board. A boundary scan checks all the incoming and outgoing signals at the borders of your circuit to ensure proper communication between components.

Built-in Self-Test

BIST involves enabling the design to perform self-testing procedures. This is useful when the design is too complex or has limited external test access.

Automatic Test Pattern Generator

ATPG is an automated algorithm that can identify potential defaults within a design by using software tools that automatically generate test patterns. It analyzes the circuit and suggests different test scenarios to uncover defects.

Conclusion

In conclusion, Design for Testability (DFT) is a crucial process in system development that focuses on making testing easier and more efficient. Incorporating Ad-Hoc and Structured techniques ensures that circuits work correctly from the beginning, saving time and resources in the long run. Do you want to learn Design for Testability? ChipEdge is a leading VLSI training institute that can help you master the art of DFT. If you are working or don’t have time to attend physical classes, you can take our VLSI courses online.