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Learn DV and DFT from Home –Without Missing a Beat DVPlus

If you’re someone looking to grow in the chip design world but need a course that fits your busy life, ChipEdge’s DVPlus online course is for you. This isn’t just another online class with endless slides. It’s a solid mix of weekend live sessions, flexible self-paced videos, and hands-on labs you can do from your own laptop.

You’ll learn everything that ensures your designs are fully testable, exactly what top semiconductor companies expect from new hires today.

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Start Date

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Training Type

Live Online Classes

Course Duration

6 months

Designed for

  • Working Professionals - VLSI/ Embedded
  • Freshers - B.Tech/ M.Tech
  • Engineering College Faculties.
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What You’ll Learn

At ChipEdge, we cover everything you need to build a strong foundation in both DV and DFT. And yes, you’ll actually use the tools professionals use.

  • Basics of Digital Design
  • SystemVerilog and UVM
  • Introduction to DFT and Scan Design
  • Scan Methodologies & On-Chip Clocking (OCC)
  • JTAG, Boundary Scan, ATPG & BIST
  • Weekly Labs + Final Capstone Project
  • ABP and AXI protocols
Contact for Course Fees

*No Cost EMI

How the Online Course Works

No matter where you’re based, this course is built to fit your schedule:

Live Weekend Classes: Learn with instructors in real-time and clear your doubts right away

Post-Recorded Videos: Rewatch topics at your own pace, any time

This course doesn’t just throw theory at you. You’ll build projects, debug real-world examples, and learn by doing.

The Tools You’ll Use

We’ll train you on tools that are widely used in the industry. You’ll feel confident stepping into interviews or internships

Synopsys VCS

For RTL simulation and verification

TetraMAX

For DFT and ATPG practice

Live debugging and simulations just like in a real job

Placement Help That Actually Helps

Getting skilled is one part; landing a job is the next, and we help with both.

  • Mock interviews and resume tips
  • Support from 200+ companies that actively hire from us
  • Virtual hiring drives and interview prep
  • A private job portal with updated openings

Who This Course is For

If any of these sound like you, you’re in the right place:

  • Final year or recent B.E./B.Tech grads
  • M.Tech/M.E. students focusing on VLSI
  • Engineers from software, embedded, or hardware backgrounds looking to switch
  • Anyone passionate about chip design and wants to break into the VLSI world

What Else You Get

Monthly VLSI webinars VLSI webinars icon
Blogs that simplify complex topics Blogs icon

Start Learning Without Leaving
Home

ChipEdge’s DVPlus Online course helps you upskill without quitting your job or moving cities. Learn in a flexible way that suits your life, and come out job-ready with skills that companies want.

Enroll in DVPlus Online Today with ChipEdge

Curriculum - Online DVPlus Course

Curriculum - Design Verification (DV)

  • Introduction to VLSI
  • Evaluation of IC Design
  • VLSI Design Styles

  • MOSFET: Structure
  • MOSFET: Principle of Operation
  • MOSFET: VI Characteristics
  • CMOS Inverter: Operations
  • CMOS Inverter: VTC

  • CMOS Technology
  • Inverter
  • Universal Gates
  • Boolean Expression
  • Stick Diagram & Layout
  • Cross Talk

  • Power Consumption in IC
  • Power Planning
  • Low Power Techniques
  • Setup
  • Hold
  • Clock Skew

  • Parasitics
  • Fanout Impact
  • PVT Corners

  • Introduction to Verilog, Top down, bottem up design, Data types, in,out, inout. Designing of basic gates. Testbench creation of basic gates.
  • Behavioural modelling, initial, always, operators, assign statements.
  • RCA, CLA
  • Control statements - if, if then else
  • Encoder & Decoders
  • Procedural statements, Simulation Regions, Delays
  • Comparator
  • System tasks
  • Latch, Flip-Flop, Blocking and Non-blocking assignments.
  • Flipflop
  • Inter & Intra delays with examples, Designing of shift registers (Digital)
  • Parameter, Universal shift register (Digital)
  • Counters Designing (Digital)
  • Counters Designing (Digital)
  • Lab session : Counter Design (Synchronous)
  • FSM : Mealy & Moore (Digital)
  • Fork - Join, Force & Release, Compiler Directives
  • Ways to avoid latches, Race condition

  • SV Testbench Architecture, Verilog Vs System Verilog, SV Data types: 2 state vs 4 state variables
  • Arrays: Fixed - Packed & Unpacked
  • Arrays: Dynamic & Associative
  • Arrays: Queues and its Usage
  • String, Structures, Unions
  • Enum Type, Events
  • Typedef Data Type and Class
  • SV Classes, Declaration, Handle & Object Creation
  • Inheritance, this, super Operator, Shallow Copy
  • Deep Copy
  • Parameterized Class, Polymorphism
  • Dynamic Casting, Scope Resolution Operator
  • IPC - Mailbox, Mailbox Methods
  • Semaphore, Events
  • Process Control (fork)
  • SV Interfaces: Interface Ports, Mod Ports
  • Clocking Blocks, Virtual Interface
  • Randomization & Constraints: Basics
  • Specifying Constraints
  • Methods in Constraints, Random Stability
  • Random Sequences, Random Case
  • Code Coverage, Functional Coverage, Cover Groups, Cover Points
  • Cover Bins, Cross Coverage
  • Coverage Options & Methods
  • Assertion: Introduction and Need for Assertion, Immediate and Concurrent Assertion
  • Assertion Statement: assert, cover
  • restrict, assume, Assertion System Task
  • Assertion System Task, Operators

  • Introduction to UVM
  • Factory Registration
  • UVM Class Hierarchy, Creating Class Memory in UVM
  • UVM Phases and Categorization
  • UVM Phases, UVM Reporting Mechanisms, Verbosity
  • Raise and Drop Objections, Copy, Print
  • Compare, Clone, Utility and Field Macros
  • $psprintf and $pformatf, Creating Multiple Instances of Class
  • In-line Commands, Factory Overriding
  • TLM Ports
  • Analysis Port, Export and Implementation
  • Blocking & Non-Blocking Methods
  • UVM Resource DB, uvm_config_db Get and Set Method with Example
  • Passing Virtual Interface using Config DB, Sequencer Driver Handshaking
  • Virtual Sequence and Virtual Sequencer, m Sequencer and p Sequencer
  • Virtual Sequence and Virtual Sequencer, m Sequencer and p Sequencer

  • APB UVM Project
  • APB SV Project

Curriculum - Design for Testability (DFT)

  • Introduction to SOC
  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics

  • Scan Architecture Overview
  • Scan Design Basics
  • Self Study / Revision
  • Scan Golden Rules
  • ICG and Lock-up Latch
  • Test Protocol DRC Check and Scan Insertion

  • Need for Scan Compression
  • Scan Compression Architecture
  • Compression Modes
  • Hierarchical Scan Design
  • Introduction to At-Speed Testing
  • On-Chip Clock Controller
  • Scan Lab 3a: Compression Ratio - Lab 1
  • Scan Lab 3b: Compression Ratio - Lab 2
  • Scan Lab 3c: Compression Lab CTL File
  • Scan Lab 3d: OCC Insertion

  • Motivation for Boundary Scan Architecture
  • Boundary Scan Design
  • Joint Test Action Group (JTAG)
  • Boundary Scan Description Language (BSDL)
  • Internal Joint Test Action Group
  • Standard Embedded Core Test

  • Single Stuck-at Fault
  • Fault Collapsing
  • ATPG Algorithm
  • TetraMAX Tool Flow
  • ATPG Lab 2: 2c - Stuck-at ATPG Pattern Generation

  • Fault Model
  • Single Stuck-at Operation
  • Delay Fault Model
  • At-Speed Testing
  • MCP and False Path
  • Bridging Fault Model
  • ATPG Types
  • ATPG DRC Rules
  • Understanding (SPF)
  • Fault Classes
  • Types of Coverage
  • ATPG Effectiveness
  • ATPG Modes
  • ATPG Graphical Viewer
  • TetraMAX ATPG Flow
  • Coverage Improvement Techniques
  • Simulation
  • Simulation Types
  • Gate Level Simulation
  • Simulation Failure
  • Fault Simulation
  • Diagnosis in ASIC Flow
  • Introduction to Diagnosis
  • Diagnosis Flow
  • Built-In Self-Test (BIST)
  • BIST Motivation
  • BIST Architecture
  • BIST in SOC, Scan vs LBIST
  • Memory BIST Architecture and Algorithms

  • Lab5b - Simulation Mismatch

  • JBI
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What Our Learners Have to Say

Everyone Will Know Something More Valuable About Education After Completing Any Type of Course in Chipedge. The Way they will Train us is excellent. The trainers train us in a well understanding manner. I am very happy and also satisfied with Chipedge institute through their Quality of Education

- Sonti Satish Goud

Best institute for vlsi physical design course. Very good lab assistance and placement opportunities. LMS procedural learning helps to understand concepts easily. Trainers are Working professionals who coach for the candidates. VPN is provided for easy access and staff are very helpful.

- Shashi Kumar

FAQ

Live interactive sessions are delivered via a virtual platform, with screen-sharing for tool demonstrations and real-time doubt clarification.

Yes. Remote access to industry tools like Synopsys VCS and TetraMAX is provided for practical sessions.

Yes. All live classes are recorded, allowing learners to revisit lessons anytime for revision.

Labs are completed using ChipEdge’s remote lab infrastructure, enabling hands-on practice from anywhere.

Yes. Flexible schedules and weekend expert sessions make it possible for working professionals to attend.

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