Offlines

Level Up in DV & DFT with ChipEdge – DV Plus

Prefer learning in a classroom? Like asking your doubts face-to-face? Then ChipEdge’s DVPlus offline course is the right place for you. It’s the same powerful DV and DFT combo course, but taught in person, in small batches, by experienced trainers.

You’ll sit in a real lab, work with real tools, and learn everything you need to crack the toughest interviews in the VLSI field.

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Start Date

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Training Type

Live Offline Classes

Course Duration

6 months

Designed for

  • B.E / B.Tech in Electronics / Electrical / Instrumentation
  • M.Tech / M.S in VLSI / Embedded Systems / Electronics / Similar
  • Working Professionals from embedded, software, or hardware domains looking to pivot
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What You’ll Learn

We don’t believe in rushing through topics. Every concept is taught with hands-on examples and backed by lab sessions.

  • Digital Design
  • Verilog and SystemVerilog
  • UVM Framework for Verification
  • Scan Design, OCC, and Scan Methodologies
  • ATPG, JTAG, BIST – Get comfortable with all the core DFT techniques
  • Final project based on a real chip verification scenario
  • ABP and AXI protocols
Contact for Course Fees

*No Cost EMI

What Happens in the Classroom

This isn’t boring blackboard teaching. You’ll be building and debugging every week:

Regular Classes (Weekdays) – Get practical exposure in person

Fully Equipped Labs – One system per student, no waiting

Group Activities – Peer learning, real teamwork, fun projects

We keep it real. If something doesn’t work in your project, you’ll learn how to fix it just like in the industry.

Tools You’ll Get Trained On

Yes, you’ll work with the tools used by actual chip designers:

Synopsys VCS

Synopsys VCS for simulation

TetraMAX

TetraMAX for test pattern generation

Guided labs and debugging exercises, every week

Why Students Love Our Offline Program

  • Real-time interaction with instructors
  • Lab environment that mirrors industry setups
  • Instant feedback and support
  • On-campus placement drives

Career Support That’s Part of the Program

From resume tips to interview training, we’ve got your back.

  • Mock interviews
  • Review sessions for your final projects
  • Hiring drives with 200+ companies
  • One-on-one guidance for job applications

Extra Perks You’ll Enjoy

Guest lectures and career talks VLSI webinars icon

Learn. Build. Get Hired – All From Our Bangalore Campus

Come join a vibrant classroom community that’s focused on helping you succeed. Learn from the ground up, build solid projects, and get into the kind of roles you’ve been dreaming of.

Apply Now for the ChipEdge DVPlus Course

Who Should Join the In-Class Program

  • Final-year and recent engineering graduates in ECE, VLSI, or similar
  • Students or professionals who prefer classroom learning
  • Anyone who wants face-to-face mentorship, labs, and group learning

Curriculum - Offline DVPlus Course

Curriculum - Design Verification (DV)

  • Introduction to VLSI
  • Evaluation of IC Design
  • VLSI Design Styles

  • MOSFET: Structure
  • MOSFET: Principle of Operation
  • MOSFET: VI Characteristics
  • CMOS Inverter: Operations
  • CMOS Inverter: VTC

  • CMOS Technology
  • Inverter
  • Universal Gates
  • Boolean Expression
  • Stick Diagram & Layout
  • Cross Talk

  • Power Consumption in IC
  • Power Planning
  • Low Power Techniques
  • Setup
  • Hold
  • Clock Skew

  • Parasitics
  • Fanout Impact
  • PVT Corners

  • Introduction to Verilog, Top down, bottem up design, Data types, in,out, inout. Designing of basic gates. Testbench creation of basic gates.
  • Behavioural modelling, initial, always, operators, assign statements.
  • RCA, CLA
  • Control statements - if, if then else
  • Encoder & Decoders
  • Procedural statements, Simulation Regions, Delays
  • Comparator
  • System tasks
  • Latch, Flip-Flop, Blocking and Non-blocking assignments.
  • Flipflop
  • Inter & Intra delays with examples, Designing of shift registers (Digital)
  • Parameter, Universal shift register (Digital)
  • Counters Designing (Digital)
  • Counters Designing (Digital)
  • Lab session : Counter Design (Synchronous)
  • FSM : Mealy & Moore (Digital)
  • Fork - Join, Force & Release, Compiler Directives
  • Ways to avoid latches, Race condition

  • SV Testbench Architecture, Verilog Vs System Verilog, SV Data types: 2 state vs 4 state variables
  • Arrays: Fixed - Packed & Unpacked
  • Arrays: Dynamic & Associative
  • Arrays: Queues and its Usage
  • String, Structures, Unions
  • Enum Type, Events
  • Typedef Data Type and Class
  • SV Classes, Declaration, Handle & Object Creation
  • Inheritance, this, super Operator, Shallow Copy
  • Deep Copy
  • Parameterized Class, Polymorphism
  • Dynamic Casting, Scope Resolution Operator
  • IPC - Mailbox, Mailbox Methods
  • Semaphore, Events
  • Process Control (fork)
  • SV Interfaces: Interface Ports, Mod Ports
  • Clocking Blocks, Virtual Interface
  • Randomization & Constraints: Basics
  • Specifying Constraints
  • Methods in Constraints, Random Stability
  • Random Sequences, Random Case
  • Code Coverage, Functional Coverage, Cover Groups, Cover Points
  • Cover Bins, Cross Coverage
  • Coverage Options & Methods
  • Assertion: Introduction and Need for Assertion, Immediate and Concurrent Assertion
  • Assertion Statement: assert, cover
  • restrict, assume, Assertion System Task
  • Assertion System Task, Operators

  • Introduction to UVM
  • Factory Registration
  • UVM Class Hierarchy, Creating Class Memory in UVM
  • UVM Phases and Categorization
  • UVM Phases, UVM Reporting Mechanisms, Verbosity
  • Raise and Drop Objections, Copy, Print
  • Compare, Clone, Utility and Field Macros
  • $psprintf and $pformatf, Creating Multiple Instances of Class
  • In-line Commands, Factory Overriding
  • TLM Ports
  • Analysis Port, Export and Implementation
  • Blocking & Non-Blocking Methods
  • UVM Resource DB, uvm_config_db Get and Set Method with Example
  • Passing Virtual Interface using Config DB, Sequencer Driver Handshaking
  • Virtual Sequence and Virtual Sequencer, m Sequencer and p Sequencer
  • Virtual Sequence and Virtual Sequencer, m Sequencer and p Sequencer

  • APB UVM Project
  • APB SV Project

Curriculum - Design for Testability (DFT)

  • Introduction to SOC
  • ASIC Flow
  • DFT Basics
  • Chip Fabrication Process
  • ATE Basics

  • Scan Architecture Overview
  • Scan Design Basics
  • Self Study / Revision
  • Scan Golden Rules
  • ICG and Lock-up Latch
  • Test Protocol DRC Check and Scan Insertion

  • Need for Scan Compression
  • Scan Compression Architecture
  • Compression Modes
  • Hierarchical Scan Design
  • Introduction to At-Speed Testing
  • On-Chip Clock Controller
  • Scan Lab 3a: Compression Ratio - Lab 1
  • Scan Lab 3b: Compression Ratio - Lab 2
  • Scan Lab 3c: Compression Lab CTL File
  • Scan Lab 3d: OCC Insertion

  • Motivation for Boundary Scan Architecture
  • Boundary Scan Design
  • Joint Test Action Group (JTAG)
  • Boundary Scan Description Language (BSDL)
  • Internal Joint Test Action Group
  • Standard Embedded Core Test

  • Single Stuck-at Fault
  • Fault Collapsing
  • ATPG Algorithm
  • TetraMAX Tool Flow
  • ATPG Lab 2: 2c - Stuck-at ATPG Pattern Generation

  • Fault Model
  • Single Stuck-at Operation
  • Delay Fault Model
  • At-Speed Testing
  • MCP and False Path
  • Bridging Fault Model
  • ATPG Types
  • ATPG DRC Rules
  • Understanding (SPF)
  • Fault Classes
  • Types of Coverage
  • ATPG Effectiveness
  • ATPG Modes
  • ATPG Graphical Viewer
  • TetraMAX ATPG Flow
  • Coverage Improvement Techniques
  • Simulation
  • Simulation Types
  • Gate Level Simulation
  • Simulation Failure
  • Fault Simulation
  • Diagnosis in ASIC Flow
  • Introduction to Diagnosis
  • Diagnosis Flow
  • Built-In Self-Test (BIST)
  • BIST Motivation
  • BIST Architecture
  • BIST in SOC, Scan vs LBIST
  • Memory BIST Architecture and Algorithms

  • Lab5b - Simulation Mismatch

  • JBI
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What Our Learners Have to Say

Everyone Will Know Something More Valuable About Education After Completing Any Type of Course in Chipedge. The Way they will Train us is excellent. The trainers train us in a well understanding manner. I am very happy and also satisfied with Chipedge institute through their Quality of Education

- Sonti Satish Goud

Best institute for vlsi physical design course. Very good lab assistance and placement opportunities. LMS procedural learning helps to understand concepts easily. Trainers are Working professionals who coach for the candidates. VPN is provided for easy access and staff are very helpful.

- Shashi Kumar

FAQ

Yes. Learners work directly on licensed Synopsys VCS, TetraMAX, and other tools in the lab.

No. Both modes follow the same DVPlus curriculum, covering DV and DFT comprehensively.

Yes. Instructors and lab assistants are available on-site for immediate guidance and problem-solving.

Typically, offline classes follow a fixed weekday or weekend schedule, depending on the batch.

Yes. Offline students participate in live mock interviews with direct feedback sessions.

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