RTL Design Course with Lint, CDC for working Professionals

Chipedge stopped offering Job Oriented VLSI courses for freshers from 2021. And offering courses for corporates and professionals only.

RTL Design Course

Learn the in-demand skill in VLSI job market and accelerate your career growth.  Live Online Sessions delivered by senior industry professionals with 10 – 20 yrs of industry experience, using Synopsys tools.

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  • Expert Trainers

  • Synopsys Tools

  • 100% Money Back Guarantee

  • Online lab Access.

  • Placement Assistance

  • Start Date24th April 2021
  • Duration:14 Weeks
  • Training Type Weekend Online

Course Overview

RTL Design course comprehensively covers the RTL Design with lint, CDC , synthesis, STA and Low Power Checks along with hands-on labs using Synopsys tools.

 

At the end of the course, the candidate will be able to do

  • Understand any given RTL in verilog/System Verilog and write small piece of  RTL as needed, like wrappers, glue logic.
  • Will be able to run Lint, CDC tools and Analyze the violations. And work with RTL team to fix the same.
  • Will be able to do logic synthesis, formal verification / LEC with DC, Formality.
  • Will be able to generate and analyze the timing reports.
  • WIll have basic knowledge of Low power techniques using UPF

Course Delivery Model:

  • Instructor-Led Live Online  training
  • Module specific Lecture sessions and Labs conducted hand-in-hand
  • Emphasis on Lab driven hands-on training aimed at building key skills
  • Weekdays: Lab support through Email and WhatsApp
  • Flexible learning with Lab Access from any where, any time.

Timings:

  • 9:30 am to 1 pm, Saturday & Sundays
  • These timings are in IST (Indian Standard Timing) time zone.

Session Details:

  • 9.30 am to 11.00 am – Lecture session
    11.00 am to 11.30 am – Tea Break
    11.30 am to 01.00 pm – Lab Session
  • The course will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in the VLSI industry on the latest technologies.

Course Fee

54,000 60,000

Exclusive of GST

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  • No Cost EMI option
  • 100% Money Back Guarantee
  • Group Discounts

Speak to our Learning Advisor for details.

VLSI Tools & Lab

Synopsys Tools

  • RTL Design / Simulations:  VCS Suite
  • Linting, CDC : Spyglass
  • Synthesis: Design Compiler
  • STA : Prime Time
  • LEC/Formal Verification:  Formality

Synopsys Spyglass, Design Compiler, Prime Time tools are market leaders with 70 to 80% market share, used by all leading semiconductor (VLSI) companies world wide.

Technology To be Used:  14nm Libraries

Lab Access:

  • Weekly 14 hours of Lab access, which can be used anytime within the week.
  • Additional lab hours per week can be purchased as per your learning needs & budget.

Who Can Attend

  • Working professionals from non VLSI industries like IT/ embedded / electronics/ teaching / any other.. who would like to switch to VLSI for career growth.
  • Embedded / FPGA Design Engineers who would like to switch to ASIC for career growth.
  • VLSI Engineers who are working in any other domain, but interested to switch to RTL design roles.
  • Corporates, who would like to get their engineers trained on RTL Design.

Placement Assistance

Chipedge provides placement help for the interested candidates as complimentary service without any extra cost.  Interested candidates need to register with the placement desk.

Why Choose ChipEdge ?

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Industry experts trainers
EXPERT TRAINERS

A meticulous and stringent selection process in handpicking the best trainers from the industry with good experience & currently working on latest technologies.

Latest Synopsys tools
SYNOPSYS TOOLS

Latest Synopsys Tools with individual Licenses for each Learner. Labs & Projects designed as per latest industry needs.

Individual attention
PLACEMENT ASSISTANCE

Complimentary Job Assistance Program without any extra cost, to help our Learners get jobs with leading VLSI Companies.

Learning Management system
FLEXIBLE LEARNING MODELS

Multiple Learning Models to choose as per your Learning Needs & budget in most cost effective way.

24x7 Lab access
ONLINE VLSI LAB

Robust VLSI Lab with latest Synopsys Tools running on high end servers and high speed internet lines with 24x7 availability

Curriculum

  • Combinational Circuits
  • Sequential Circuits
  • Finite State Machines
  • Frequency Division
  • Setup/Hold time and violations
  • Advanced Design Issues: Metastability, Noise Margins, Power, Fan-out, Timing Considerations
  • FIFO Depth Calculation
  • Introduction to Verilog & Modeling Styles with Examples
  • Some more examples (Encoder, comparator, etc) and their Verification
  • sequential  – DFF, Shift registers and their Verification
  • Tasks and Functions
  • Inter/Intra Assignment, Blocking and Non-Blocking Assignments
  • Parameters and Parameterised modules
  • Coding styles in FSMs
  • RTL for synthesis
  • RTL Coding guidelines
  • Introduction to ASIC Design Flow
  • Role of Front end design in ASIC Design Flow.
  • Role of RTL Design in Front End Design Flow.
  • Role of EDA Tools in Front End Design / ASIC Design flow.
  • Purpose of RTL & Linting
  • How does it work?
  • Typical Lint Targets
  • Lint Example
  • SpyGlass Tool Flow
  • SpyGlass Design Read
  • Goal Selection & Setup
  • Run Analysis & Debug
  • SpyGlass Tool Setup
  • CDC Basics
  • Clock Domain & Clock Groups
  • CDC Problems & Solutions
  • CDC Synchronization Techniques
  • Issues in CDC flow
  • Constraints vs Waivers
  • Capturing Design Intent in CDC Constraints
  • SpyGlass Tool setup
  • Run Analysis and Debug
  • Introduction to Synthesis
  • Synthesis Flow
  • Constraining the design for timing, area, power
  • Creating timing constraints in SDC format
  • Understanding & Exploring .lib libraries
  • Synthesize Design
  • Timing Analysis & Optimization
  • Generate reports, Analyze and debug results
  • STA overview & concepts
  • Clocking – Handling clock muxes, clock dividers
  • Generated clocks, Clocking Exceptions
  • Timing Exceptions
  • Generate & analyze timing reports
  • Timing ECOs generation
  • Loading reference & implemented design
  • Understanding & Matching compare points
  • Verifying design & interpreting results
  • Debugging the Non Equivalents

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Demo Videos

Video Reviews

Learner Reviews

FAQs

Training is delivered in Instructor-Led Virtual Class Room mode, on weekends. To attend the live sessions,  you need to login to the chip edge e-learning portal. For Lab access, you will connect to the ChipEdge VLSI lab through a VPN.

Timings:

9:30 am to 1 pm, Saturday & Sundays

These timings are in IST (Indian Standard Timing) time zone.

Session Details:

9.30 am to 11.00 am – Lecture session

11.00 am to 11.30 am – Tea Break

11.30 am to 01.00 pm – Lab Session

The course  will be delivered by Senior VLSI Engineer with lab assistance from junior VLSI Engineer. Both are currently working in VLSI industry on latest technologies.

Chipedge trainers are typically having 10 to 20  years of VLSI industry experience and currently working in the latest technologies. They are typically project leads or project managers and are selected for their domain expertise, passion for sharing knowledge as well as good teaching skills.

They are available on weekends only, during class hours for live interaction.

Instructor led online courses on weekends, are primarily designed for working professionals who want to upskill themselves.

With shrinking technology nodes and increasing complexity of Chips, engineers are required to enhance their skills to stay relevant in their careers and increase their productivity.

Online courses can help you learn new skills as well as increase your knowledge in the area you are currently working. Skills that take years to master in the workplace can be imbibed in weeks using our combination of theory classes, hands-on training sessions, projects. As these sessions are delivered by Senior VLSI engineers with 10 to 20 years of industry experience, learning from their experiences is a big takeaway from these courses.

Considering time constraints for all working professionals, you can attend these courses from home.

We use the latest versions of Synopsys Tools, with a  dedicated tool license for every trainee during the lab/project work. 28nm libraries are used for labs, projects.

Synopsys tools are used by the majority of product / MNC companies in the semiconductor(VLSI) industry worldwide, not just in India.

Lab Access is provided through VPN. This gives the flexibility to do labs anytime, anywhere at your convenience. All you need is a good broadband connection and a laptop.

It varies as per the course duration (short/long). please check the “Lab”  tab, in course pages. Our course counselors can help you as well.

We do have installment options for some courses. And EMI option is available through our partner organizations, who provide loans for training programs.  please check with our Course Counsellors.

Course completion certificates will be provided, whoever meets the course completion criteria.

Chipedge provides placement help to interested candidates, who need to register with placement desk.  Its complimentary service without any fee / cost.

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