RTL Design Online Course Overview RTL Design Engineer’s scope of work has changed in the last few years. It has changed mostly into tool intensive job than pure coding. Most of the development of new chips is driven by integrating readily available Design IPs, than developing fresh RTL Codes. RTL Design Engineer nature of work includes RTL Coding using Verilog/System Verilog, RTL integration which involves writing glue logic as needed for integrating the IPs, tool intensive works mainly on Linting, CDC (clock domain crossing) checks on a daily basis. Some roles include Synthesis, STA (Static Timing Analysis), LEC (logical equivalence checks) tasks as well. RTL Design Course comprehensively covers micro architecture, digital design partitioning, RTL Development using synthesis friendly verilog coding styles. Followed by Linting using Spyglass tool, which exhaustively checks various rules and flags errors/warnings for fixing. CDC checks are done with SpyGlass for checking various CDC rules. RTL Design in VLSI covers various rules along with examples and how to analyze, fix them. Each module of RTL Design Online Course has associated hands on labs and multiple projects, to give good exposure to industry complexity. Synopsys SpyGlass tools is widely used in the industry as sign off tool for LINT, CDC checks.
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