• Number System, Boolean Algebra,
• SOP and POS, K-Map,
• Combinational circuits, Sequential circuits
• Finite State machines,
• Frequency Division,
• Setup and Hold time checks,
• Advance Design Issues: Metastability, Noise Margins, Power, Fanout, Timing Considerations,

Verilog HDL

• ASIC Flow, Module, declaration and Instantiation, Components of simulation, Procedural blocks, Lexical convections.
• Data types, Module Parameters, Operators, Primitives, Functional. representation in Verilog.
• Arrays, Memories, System tasks, compiler Directives, Continuous and Procedural Assignments, Examples of Blocking and Non-blocking statement.
• Race Condition, Timing Controls Sequential and Parallel Blocks, Conditional Statements, loops Statements.
• Task, Functions, Difference between task and Function.

Verification Lab

Combinational circuits

• 2×1 Multiplexer, 4×1 Multiplexer
• 4:2 Decoder
• Half Adder and Full Adder
• Priority encoder
• Sequential circuits
• D-ff
• SISO
• Counters
• Design and Verification of FSM (1 FSM to be done by the students for final assessment).

SV Testbench Architecture, Verilog vs System Verilog, SV Data types: 2 state vs 4 state variables, Dynamic Arrays, Associative Arrays, and its Usage.

Strings, Unions, Structures, Enumerated data Types, Events.

SV Interfaces: Interface ports, Mod ports, Clocking blocks, Virtual Interface, Program blocks.

SV Class, Inheritance, this operator, super operator, shallow copy, deep copy, parameterized classes, typedef classes, polymorphism, abstract class, encapsulation, dynamic casting, scope resolution operators.

IPC: Event, Mailbox, Semaphores Randomization & Constraints: Basics, specifying constraints, methods in constraints, random stability, random sequences, and random case.