Sanity Checks In VLSI: Better Vision For Better Connection

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Sanity Checks In VLSI: Better Vision For Better Connection

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Sanity checks in VLSI are an essential step for physical design engineers to ensure that the inputs are proper and consistent. Any errors in the input files may cause trouble later on. Hence, it is critical to perform sanity checks early on, before loading the design into the PnR tool and before starting the floor plan.

What is the need for sanity checks in VLSI?

Sanity checks in VLSI serve as a checkpoint to decide whether the testing for design-build may proceed or not. The main purpose of this testing is to ensure that the changes or planned features are operating as intended. If the sanity test fails, the testing team rejects the design-build to save time and money. Before engineers begin their physical design cycle, they must run some sanity tests. Sanity checks guarantee that the information obtained from multiple teams, such as the synthesis team and the library team, is proper. If they fail to do these tests, they may have problems at a later stage.

 

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The input files to be checked during sanity checks include:

Netlist: 

Netlist consistency must be confirmed. This check examines the currently loaded netlist for inconsistencies and reports them.

SDC Files: 

Before beginning the design, the SDC file must be verified. Some of the most prevalent SDC file issues are:

  • Unrestricted route
  • The clock reached all synchronous components.
  • Registers powered by several clocks
  • Endpoint with no constraints
  • A port’s input/output delay is missing.
  • A port’s slew or load limitation is absent.
  • Clock definition is missing.

Library Files: 

In library check, we basically evaluate the libraries before beginning the physical design by comparing the physical and logical libraries. It also examines the quality of both libraries and indicates any errors. The cells used in the design must be present in both the logical and physical libraries.

Pre Placement Sanity Checks in VLSI Design include:

  • Undriven Input Ports
  • Timing
  • Floating pins in netlist
  • Checking physical constraints
  • Pin direction mismatch
  • Unloaded output ports
  • Unconstrained pins
  • PG grid check


Conclusion

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