What Is Synthesis In VLSI
What is synthesis in VLSI is a question that is expected to be answered by a VLSI student. Nevertheless, it […]
RTL Design – Lint & CDC
Design Verification
What is the Role of Formal Verification in VLSI?
ASIC project life cycle stages like front-end verification, logic synthesis, post routing checks, and ECOs all employ formal verification. However,
General
Impact of Technology Shrinking
How Our Lives are Affected by Micro and Nanotechnology Micro and nanotechnologies both aim to reduce the size of items
General
What is Linting in VLSI?
Unlike the lint on our clothes, lint in VLSI is the removal of non-portable or suspicious code. It is a
Design for Test
Types of Testing in Design for Testability?
Design for testability(DFT) in VLSI is to reduce the time and effort necessary to generate test vector sequences for testing
Design for Test
Pursue a Career in DFT in the VLSI Domain after Graduation?
DFT stands for Design For Test. This course lasts one year and has a syllabus separated into two semesters. It
Design Verification
Interesting Uses of Python, TCL and Perl
Dynamic languages are renowned for rapid application prototyping or for “duct tape” solutions to connect systems. Most people think that
General
What is Scripting language and it’s usage for VLSI engineer
To be successful, every complicated design project will place high importance on quality as well as time to market. So
General
Full Custom Design in VLSI: The New Innovation!
Full-custom design in VLSI is a method of creating integrated circuits that specifies the architecture of each individual transistor as
Design Verification
Why is UVM Verification Critical for Success in Chip Design?
UVM stands for Universal Verification Methodology. It is a standardized methodology for verifying integrated circuits, ASICs, and SoC architectures. It
