Design Verification (DV) Trainer / Mentor
We’re on the lookout for seasoned Design Verification (DV) Trainer / Mentor who want to give back to the industry by mentoring the next generation of engineers. Whether you want to engage full-time or dedicate your weekends, this role gives you the chance to share your expertise and stay closely connected to VLSI design.
Key Responsibilities:
- Deliver full-time Design Verification courses, including lectures, lab sessions, and project guidance.
- Prepare learners to be industry-ready by building strong skills in SystemVerilog (SV), UVM, and Digital Design concepts.
- Facilitate labs and project execution with support from lab instructors, ensuring hands-on learning.
- Regularly update course content, lab exercises, and projects to reflect latest verification methodologies and industry trends.
- Mentor students on technical communication, teamwork, and professional practices in project environments.
- Manage course schedules, batch timelines, and coordinate resources for smooth and efficient training delivery.
For Candidates from Industry Background:
- Experience: 2–5 years in Design Verification, with a valid Professional DV Certificate.
- Expertise: Strong proficiency in Verilog, SystemVerilog, UVM, and industry-standard verification methodologies.
- Tools Experience: Hands-on experience with EDA tools from Synopsys/ Cadence/ Mentor Graphics.
- Protocols: Familiarity with standard bus and communication protocols used in the semiconductor industry.
- Technical Strengths: Good understanding of Digital Design, Verilog HDL, and CMOS fundamentals.
- Attributes: Self-motivated, proactive, capable of driving projects independently, and mentoring junior engineers effectively.
For Candidates from Academic Background:
- Experience: 2–20 years of teaching or research experience in VLSI, Digital Design, or Design Verification.
- Knowledge: Strong understanding of Digital Design, Verilog HDL, and CMOS concepts.
- Tools Exposure: Awareness of EDA tools (Synopsys, Cadence, Mentor Graphics) – (Candidates without hands-on experience will be provided training by ChipEdge to gain tool proficiency.)
- Attributes: Self-driven, quick learner, able to mentor students and collaborate effectively in a team-oriented environment.
Preferred Qualifications:
- Prior academic teaching experience in VLSI Design / Verification.
- Minimum 3+ years of relevant experience in Design Verification or related domains.
Why Join ChipEdge?
- Opportunity to train and mentor aspiring VLSI Design Verification engineers.
- Access to industry-grade tools and projects aligned with current semiconductor practices.
- Collaborative and growth-oriented environment focused on continuous learning and innovation.
How to Apply: Interested candidates can send their resume and a cover letter to hr@chipedge.com with the subject line “Design Verification (DV) Trainer / Mentor“
About ChipEdge: ChipEdge is a premier VLSI training company dedicated to bridging the gap between academic knowledge and industry requirements. Our mission is to provide high-quality training programs that empower students and professionals with the skills needed to excel in the semiconductor industry. We strive to make a significant impact in imparting VLSI skills, an emerging sunrise technology and business, in India and across the globe.
Join us in our journey to educate and inspire the next generation of Electronics Engineers!
