UVM stands for Universal Verification Methodology. It is a standardized methodology for verifying integrated circuits, ASICs, and SoC architectures. It is majorly based on the Open Verification Methodology (OVM).
What is UVM and why is it important?
UVM is a Standard Verification Methodology that uses SystemVerilog structures to provide a fully complete testbench to ensure that the Design Under Test (DUT) is functionally accurate. It is an IEEE standard/methodology that is based on the System Verilog programming language. UVM is built on OVM and incorporates essential features from VMM and TLM (by Open SystemC Initiative).
UVM verification may be thought of as a reusable, scalable, and adaptable pre-defined verification testbench architecture.
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What Does UVM Verification Include?
UVM is an open source project that includes:
UVM makes use of System Verilog and Object Oriented Programming (OOP), which employs concepts such as Class, Objects, Inheritance, and Polymorphism.
Although the architecture of UVM is pre-defined, it can be easily customized. Similar to how a child would play with Lego building blocks, the user has some freedom to use the components as needed for the project. For example, in accordance with standard UVM TB architecture, an agent should be instantiated inside the environment, and the agent should include a driver, monitor, and sequencer.
However, the user has the option of launching the driver, monitor, and sequencer directly from the UVM environment, without the need to launch an agent. As needed, the user can additionally experiment with analysis ports and analysis FIFOs.
- A library of foundation classes for creating testbench components (Agent, Sequencer, Driver, Monitor, Scoreboards, Environment class, and so on);
- A factory for creating and substituting objects.
- Transaction Level Modeling (TLM) for communication between verification components.
- Verification phases for coordinating concurrent operations
- A reporting system for publishing and logging findings in a consistent manner
- Macros to generate UVM code semi-automatically.
What is the purpose of UVM Verification?
UVM aims to improve flexibility and code reuse by allowing the same testbench to be configured in a variety of ways to construct new components and give varied stimuli. It is suggested that these new user-defined configuration classes be derived from UVM objects.
Unlike previous methodologies developed independently by simulator vendors, the UVM class library brings much automation to the SystemVerilog language, such as sequences and data automation features (packing, copy, compare), and is an Accellera standard with support from multiple vendors: Aldec, Cadence, Mentor Graphics, Synopsys, and Xilinx Simulator (XSIM).
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