The Mechanism Behind Linting in VLSILike any other tool, linting in VLSI has a set of rules that must be followed. A condition that must be checked on your design is referred to as a rule. The required rules can be enabled and disabled as needed by the user. When these rules are applied to the design, if the design source code violates one of the rules, a violation is recorded. Linting offers early-stage designers insights into RTL code. Linting saves time by discovering coding errors and advising a remedy early in the design process, hence enhancing the trust of the RTL Design Engineer.
Steps in the Process
- Modify the configuration or define the ruleset
- The user can alter the configuration settings and tweak the rules by enabling or disabling them according to their needs
- Source rules and invoke the tool
- Analyze the Plan
- Create a report
Functions of Linting in VLSIThe lint in VLSI performs a number of checks to ensure that an RTL design is of high quality. Some examples are as follows:
- Is there a design with any combinational loops?
- Is there anything in the design that can’t be synthesized?
- Are there any nets in the design that aren’t powered but are loaded?
- Check if you have any multi-driven ports or networks in your design?
- Is there anything in the design that isn’t supposed to be there?
The following is a List of Lint Tools in VLSI
- SPYGLASS from Synopsys.
- Cadence’s GASPER GOLD
- ALINT PRO is an Aldec product.
- Mentor Graphics