Latch-up in VLSI is a short circuit/low impedance channel generated between the power and ground rails of a MOSFET circuit, resulting in high current leading to IC damage. It is caused by the interaction of parasitic PNP and NPN transistors (BJTs). This results in a structure that resembles a Silicon Controlled Rectifier (SCR). These create a positive feedback loop by short-circuiting the power and ground rails, resulting in excessive current and perhaps causing damage to the device.
How Does Latch-Up Form?
The parasitic structure is commonly equivalent to a thyristor (or SCR), a PNPN structure that functions as a PNP and an NPN transistor stacked next to each other. When one of the transistors conducts during a latch-up, the other also begins to conduct.
They both maintain saturation for as long as the structure is forward-biased and some current flows through it- which is normal until the power is turned off. The SCR parasitic structure is produced on the output drivers of the gates as a component of the totem-pole PMOS and NMOS transistor pair.
What is the Cause for Latch-Up in VLSI?
- Usually, latch-up caused by a positive or negative voltage spike on an input or output pin of a digital device that exceeds the rail voltage by more than a diode drop is a typical cause of latch-up. The latch-up in VLSI does not have to occur between the power rails; it can occur anywhere where the necessary parasitic structure exists.
- Another cause is that the supply voltage exceeds the absolute maximum rating, frequently caused by a transient spike in the power supply. It causes an internal junction to fail. This is common in circuits that employ various supply voltages that do not power up in the correct order. This results in voltages on data lines exceeding the input rating of devices that have not yet attained a nominal supply voltage.
- An electrostatic discharge can also create latch-ups.
- Ionizing radiation is another typical source of latch-ups, making it a serious concern in electronic devices meant for space (or extremely high-altitude) applications.
- Latch-ups can also be caused by high-power microwave interference. At increasing temperatures, both CMOS and TTL integrated circuits are more prone to latch-up.
Prevention Techniques for Latch-Up in VLSI
Latch-up resistant chips incorporate an insulating oxide trench, preventing the formation of parasitic SCR structures between NMOS and PMOS transistors. Lightly doped epitaxial layers on heavily doped substrates reduce latch-up susceptibility. Silicon-on-insulator devices inherently resist latch-up, as each transistor has its tap connection, avoiding low-resistance connections between the tub and power supply rails.
Conclusion
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