VLSI physical verification is a critical step in the chip design process that ensures the correctness and reliability of the physical layout of integrated circuits. The process involves checking the design against a set of rules and criteria, known as design rules, to ensure that the final product functions as intended. Physical verification is important in the VLSI design process as it helps identify potential errors, such as incorrect wiring or other layout-related problems, that can cause manufacturing defects, impact the performance of the circuit, or lead to device failure. The physical verification process checks for compliance with design rules, such as spacing, metal layers, alignment, via placement, short circuits, and open/float pins. This procedure in the design ensures that the design meets the manufacturing requirements after clearing all the errors.
Steps Involved In The Physical Verification Process
VLSI physical verification is a crucial step in the chip design process. It involves verifying the physical layout of integrated circuits against a set of rules and criteria, known as design rules. Physical Verification consists of all the signoff checks such as design rule checks, layout versus schematic, Electric rule checks, resistance checks. All these checks should be clean and send IP for tapeout. Here are the general steps involved in the VLSI physical verification process:
Design Rule Check (DRC)
In this step, the design is checked for basic design rules violations, such as minimum spacing, minimum width, and minimum area. The DRC tool ensures that the design meets the manufacturing requirements and provides a report highlighting any violations.
Layout vs. Schematic (LVS)
In this step, the layout is compared to the schematic to ensure that they are consistent. The LVS tool checks the connectivity between the layout and the schematic and generates a report highlighting any discrepancies. Some of the problems encountered in the LVS are missing global nets, unlikely assignments (assigns), syntax mismatch between rtl vs tools in physical verification and flipped buses.
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Electrical Rule Check (ERC)
In this step, the design is checked for electrical rule violations, such as signal integrity and power supply noise. The ERC tool analyzes the design and generates a report highlighting any violations.
Design for Manufacturability (DFM)
In this step, the design is optimized for manufacturing by ensuring that it meets the foundry’s manufacturing process requirements. The DFM tool analyzes the design and generates a report highlighting any violations.
What is the Need for Physical Verification?
The need for physical verification arises from the increasing complexity of semiconductor devices and the high cost associated with chip fabrication. Physical verification ensures that the final product functions as intended by verifying the correctness and reliability of the physical layout of the integrated circuits.
Physical verification tools are used to automate the verification process, enabling designers to quickly detect and correct any layout errors. These tools use sophisticated algorithms and computational techniques to analyze the design and identify any errors that need to be fixed. They also provide designers with detailed reports that help them understand the nature and severity of the errors.
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