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20-01-2019
Analog Layout Design

Duration: 15 Weeks (Sun)

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02-02-2019
ASIC Design Verification

Duration: 18 weeks (Sat)

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09-02-2019
Synthesis Sign-Off STA and LEC

Duration: 8 Weeks(Sat)

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23-02-2019
DFT (SCAN & ATPG)

Duration: 14 Weeks (Sat)

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03-03-2019
Physical Verification

Duration: 11 Weeks (Sun)

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10-03-2019
Physical Design

Duration: 15 Weeks (Sat)

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19-03-2019
Asic Design Verification {Full-Time}

Duration: 4.5 Months

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23-03-2019
Verification using UVM

Duration: 05 Weeks(Sat)

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24-03-2019
CMOS Analog Circuit Design

Duration: 08 Weeks(Sat)

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18-05-2019
Low Power Implementation(PD) using UPF

Duration: 4 Weeks(Sun)

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17-02-2019
TCL Scripting

Duration: 03 Weeks(Sat)

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23-02-2019
High Speed IO Circuit Design

Duration: 08 Weeks(Sat)

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16-03-2019
Verification using System Verilog

Duration: 06 Weeks(Sat)

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