Congratulations to Anushree Chandran for placement in Synopsys in Physical Design    Congratulations to Bandreddi Venkateshwar Rao and Kishor Naik for placement in Aricent in Physical Design    Congratulations to Chaitrashree and Prathamesh Kulkarni for placement in JGD Tech in Analog Layout    Congratulations to Hemavathy and Suman for placement in Aricent in Physical Design    Congratulations to Jagan for placement in Wipro in Physical Design    Congratulations to Jithesh for placement in Laksh Semi in Physical Design    Congratulations to Juturu Muruli Shankar and Shreyas BK for placement in Aricent in Physical Design    Congratulations to Shubha for placement in Sibot Technologies in Analog Layout    Congratulations to Manoj Chowdary and Payam Nagesh for placement in Aricent in Physical Design    Congratulations to Neeraj Sharma for placement in Black Pepper in Analog Layout    Congratulations to Podila Keerthi and Praveen Chennam for placement in Aricent in Physical Design    Congratulations to Navyatha for placement in Altran in Physical Design    Congratulations to Sneha Rathod for placement in Exiger in Physical Design    Congratulations to Surabhi and Abhishek for placement in Aricent in Physical Design
Lay Desai, M-Tech Intern, Intel Corporation

Lay Desai, M-Tech Intern, Intel Corporation

I have done B.E. in E&C from SCET, Surat, Gujarat. M.Tech in VLSI Design from VIT University, Chennai Campus.Have 1 year of experience as FPGA Design Engineer at Mistral Solutions pvt ltd, Bangalore.Did internship...

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