{"id":42352,"date":"2026-09-21T09:20:25","date_gmt":"2026-09-21T09:20:25","guid":{"rendered":"https:\/\/chipedge.com\/resources\/?p=42352"},"modified":"2026-09-21T09:20:25","modified_gmt":"2026-09-21T09:20:25","slug":"dft-in-vlsi-what-engineers-do-why-role-is-indispensable","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/","title":{"rendered":""},"content":{"rendered":"

What DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable<\/b><\/h2>\n

Every chip that reaches a customer was tested after fabrication. The test that caught defective chips before they shipped was made possible by work done long before fabrication began.<\/span><\/p>\n

That work belongs to the <\/span>DFT engineer<\/strong>.<\/span><\/a><\/p>\n

DFT in VLSI stands for Design for Test<\/strong><\/a> or Design for Testability. The discipline exists because a chip’s internal logic is physically inaccessible from its external pins during normal operation. Without DFT structures built into the design, manufacturing defects deep inside the chip would go undetected. Defective chips would reach customers. Field failures, recalls, and warranty costs would follow.<\/span><\/p>\n

DFT engineers prevent this by designing test infrastructure into the chip during the design phase itself, ensuring that every manufactured unit can be thoroughly and efficiently tested before it leaves the foundry. This article explains what DFT engineers actually do across the lifecycle of a VLSI project and why their role cannot be separated from the chip design process.<\/span><\/p>\n

Why DFT Engineering Exists as a Separate Discipline in VLSI Development<\/b><\/h3>\n

DFT became a separate engineering discipline as chips grew complex enough that functional testing at the chip boundary became insufficient.<\/span><\/p>\n

In early semiconductor development, engineers tested chips by applying functional input patterns at the chip’s external pins and observing the outputs. For simple chips with a small number of internal nodes, this approach detected most manufacturing defects.<\/span><\/p>\n

Modern chips have billions of transistors and logic structures buried deep inside the chip that are completely invisible from the external pins during normal operation. A stuck-at fault in the middle of a deep logic cone may never propagate to an output under any realistic functional input. A defective memory bitcell may only fail under specific access patterns that functional testing never exercises.<\/span><\/p>\n

Scan-based DFT solved this problem by building a shadow test infrastructure directly into the chip. By converting flip-flops into scan-capable elements and connecting them into shift register chains, DFT engineers create a mechanism that allows test equipment to directly observe and control every flip-flop in the design, regardless of its physical location. This makes comprehensive manufacturing test possible for designs of any complexity.<\/span><\/p>\n

The methodology, the tools, and the expertise required to do this effectively are specialised enough that DFT has developed into a dedicated engineering discipline with its own career track, its own tool ecosystem, and its own set of engineering challenges.<\/span><\/p>\n

When DFT Engineers Get Involved in a VLSI Project and Why Timing Matters<\/b><\/h3>\n

DFT engineers get involved at the very beginning of a <\/span>chip project<\/a><\/strong>, not after the design is complete.<\/span><\/p>\n

This timing is not optional. It reflects a fundamental constraint of the discipline. DFT structures affect the RTL, the synthesis netlist, and the physical implementation of the chip in ways that must be planned from the start of the design process. Attempting to retrofit DFT onto a completed design is far more expensive than integrating it from the beginning, and the quality of the resulting DFT implementation is almost always lower.<\/span><\/p>\n

During the specification phase, DFT engineers review the chip architecture for testability implications. They identify potential DFT challenges created by architectural choices, such as internally generated clocks that complicate scan operation, multi-voltage domains that require power-aware test structures, and embedded memory arrays that need BIST infrastructure.<\/span><\/p>\n

During <\/span>RTL coding<\/strong>,<\/span><\/a> DFT engineers review the RTL for compliance with DFT guidelines and work with the RTL team to resolve structures that will create problems during scan insertion or limit ATPG coverage. Catching and fixing these issues during RTL development costs a fraction of what it costs to fix them after synthesis.<\/span><\/p>\n

Late DFT involvement consistently produces chips with lower fault coverage, more design iterations, and more schedule pressure than projects where DFT engineers were engaged from the beginning. This is why the role is not a post-design activity but an integral part of the design process from day one.<\/span><\/p>\n

What DFT Engineers Are Responsible for During the Front End Design Stage<\/b><\/h3>\n

DFT Architecture Planning<\/b><\/h4>\n

DFT architecture planning involves making the high-level decisions about how testability will be implemented across the chip before any specific structure is inserted into the design.<\/span><\/p>\n

This includes deciding how many scan chains the design will have and how they will be organized across the chip’s physical area, what test clock scheme will be used to operate the scan chains without violating timing requirements, how the test mode control signals will be distributed, how BIST will be implemented for embedded memory arrays, and how the JTAG boundary scan interface will be structured.<\/span><\/p>\n

These architecture decisions have cascading implications for area, power, and routing resources in the physical implementation. A DFT architect who makes good decisions at this stage produces a design that implements testability efficiently. One who makes poor decisions creates <\/span>physical design<\/a><\/strong> constraints that are expensive and time-consuming to accommodate.<\/span><\/p>\n

Scan Structure Definition<\/b><\/h4>\n

Scan structure definition translates the DFT architecture into specific implementation guidance for the scan insertion tool.<\/span><\/p>\n

This includes specifying which flip-flop types will be replaced with scan-capable equivalents, how the scan chain connections will be organized to balance chain lengths across the test I\/O pins, what test clock exclusions are needed to prevent scan interference with specific functional paths, and what test mode controls are required to operate the scan infrastructure correctly.<\/span><\/p>\n

During synthesis, these specifications are implemented by tools like Synopsys DFT Compiler, which performs the scan insertion automatically based on the DFT engineer’s specifications. After insertion, the DFT engineer verifies that the resulting scan structure is correct through simulation before ATPG begins.<\/span><\/p>\n

What DFT Engineers Do During and After Physical Design<\/b><\/h3>\n

Scan Chain Reordering<\/b><\/h4>\n

After the physical design team completes <\/span>placement<\/a><\/strong>, scan chain reordering is often necessary to reduce the routing resources consumed by scan chain connections.<\/span><\/p>\n

The initial scan chain order determined during scan insertion is based on the logical netlist without knowledge of where cells will be placed physically. After placement, adjacent cells in the scan chain may be placed far apart on the chip, creating long routing detours for the scan connections. Reordering the scan chain to connect physically proximate cells improves routing efficiency and reduces congestion.<\/span><\/p>\n

DFT engineers work with the physical design team to perform this reordering in a way that maintains correct scan operation while reducing the routing burden. The specific connections changed during reordering must be verified in simulation after the change to confirm that the scan chain continues to operate correctly.<\/span><\/p>\n

DFT Timing Verification<\/b><\/h4>\n

DFT timing verification confirms that the scan chain can operate correctly at the required test clock frequency after the physical parasitics of the actual routing are known.<\/span><\/p>\n

Scan muxes add input capacitance to flip-flop data inputs, which affects hold time sensitivity on those paths. Test clock distribution paths have different timing characteristics from functional clock paths. After routing, the actual parasitic values of the scan connections and test clock paths must be analyzed to confirm that the scan chain meets its timing requirements under the conditions defined by the test protocol.<\/span><\/p>\n

DFT engineers review the post-route timing analysis specifically for test mode paths, identifying and resolving any violations in the scan clock distribution or scan data paths that would prevent correct scan operation at the target test frequency.<\/span><\/p>\n

How DFT Engineers Work with ATPG Tools to Generate Test Patterns<\/b><\/h3>\n

ATPG is the process by which the test patterns applied to manufactured chips during production testing are generated. DFT engineers own this process from setup through delivery of the final pattern set.<\/span><\/p>\n

The process begins with importing the scan-inserted gate-level netlist into the ATPG tool, Synopsys TetraMAX being the most widely used platform. The DFT engineer<\/strong> defines the test protocol, specifying the sequence of scan shift and capture operations that the tester will execute, the clock frequencies to be used for shift and capture, and the test mode configurations required to access different parts of the design.<\/span><\/p>\n

Pattern generation runs automatically once the setup is complete, with the ATPG tool attempting to generate patterns that activate and observe each targeted fault. The resulting fault coverage report shows what fraction of the design’s faults are detected by the generated patterns.<\/span><\/p>\n

The DFT engineer analyzes the coverage report in detail. Faults that are not detected fall into two categories. Some are structurally untestable because of the design’s architecture, which may be acceptable. Others are untestable because of DFT implementation issues that can be corrected to improve coverage. Distinguishing between these categories and resolving the correctable ones requires the diagnostic capability that production ATPG experience develops.<\/span><\/p>\n

The final deliverable from the <\/span>ATPG <\/a><\/strong>process is the validated test program delivered to the test team, which will apply the patterns to manufactured chips using automated test equipment during production testing.<\/span><\/p>\n

How DFT Engineers Collaborate with RTL Verification and Physical Design Teams<\/b><\/h3>\n

DFT engineers work with multiple teams across the chip development lifecycle and must communicate effectively in each team’s technical vocabulary.<\/span><\/p>\n

With the RTL design team, DFT engineers conduct DFT compliance reviews during RTL development, identifying coding patterns that will create scan insertion problems or limit ATPG coverage. They explain what needs to change in the RTL and why the change is necessary for testability, and they verify that the corrections have been made correctly before synthesis.<\/span><\/p>\n

With the verification team, DFT engineers define the testbench requirements for verifying DFT structures. The scan chain must be verified to operate correctly in simulation. BIST controllers must be verified to implement the intended test algorithm. JTAG interfaces must be verified to comply with the IEEE 1149.1 standard. DFT engineers specify what these simulations need to demonstrate and review the results to confirm DFT structural correctness.<\/span><\/p>\n

With the physical design team, DFT engineers communicate the physical constraints that DFT implementation requires. Scan chain routing budgets, BIST controller placement proximity to memory macros, test clock distribution routing requirements, and test I\/O pin assignments all have physical design implications that must be communicated clearly and accommodated in the implementation.<\/span><\/p>\n

What Happens When DFT Is Not Given Enough Attention in a VLSI Project<\/b><\/h3>\n

The consequences of inadequate DFT planning are specific and expensive.<\/span><\/p>\n

Insufficient scan coverage means that a significant fraction of manufacturing defects are not detected by the test program. Defective chips pass production testing and reach customers. Field failure rates are higher than they should be. Warranty costs increase. In safety-critical applications like automotive or medical devices, undetected defects can have consequences beyond financial cost.<\/span><\/p>\n

Late DFT insertion that was not planned from the beginning of the project typically requires design rework that delays the tape-out schedule. RTL that was not written with DFT compliance in mind requires modification after synthesis, which may require re-verifying the affected blocks. Physical design that did not account for scan chain routing requirements may need to be revised to accommodate scan connections that were not anticipated in the routing resource planning.<\/span><\/p>\n

Low fault coverage discovered late in the project creates pressure to either accept inadequate test quality or delay tape-out while the DFT team resolves the coverage gaps. Neither outcome is acceptable in a well-managed chip program, which is why DFT architects who can prevent these situations are consistently valued on semiconductor engineering teams.<\/span><\/p>\n

How DFT Engineers Use Coverage Metrics to Validate Test Quality<\/b><\/h3>\n

Fault coverage is the primary metric DFT engineers use to validate the quality of the test program they have developed.<\/span><\/p>\n

The fault coverage percentage represents what fraction of all possible faults in the design’s fault model are detected by the generated test patterns. A fault coverage of ninety-five percent means that five percent of possible faults would not be detected if they were present in a manufactured chip. How much coverage is acceptable depends on the application. Automotive chips targeting functional safety certifications like ISO 26262 have stringent minimum coverage requirements. Consumer chips may have lower but still meaningful thresholds.<\/span><\/p>\n

Beyond the overall coverage number, DFT engineers analyze coverage by fault category and by design region. Low coverage in a specific block indicates a DFT implementation problem in that block that needs investigation. Low coverage for a specific fault model indicates that the scan architecture may not be providing adequate observability for that fault type.<\/span><\/p>\n

Transition fault coverage is increasingly important alongside stuck-at coverage as technology nodes shrink and timing-related manufacturing defects become more common. DFT engineers develop pattern sets that target both fault models and analyze coverage for each to confirm that the combined test program is adequate for the design’s manufacturing quality requirements.<\/span><\/p>\n

What a Typical Day Looks Like for a DFT Engineer in a Semiconductor Company<\/b><\/h3>\n

A DFT engineer’s typical day depends on which phase of the chip project they are currently working on, but several activities recur across most phases.<\/span><\/p>\n

During the front-end phase of a project, a typical day involves reviewing RTL changes from the design team for DFT compliance issues, running scan insertion checks on recently synthesized blocks, and investigating coverage gaps in ATPG runs that were queued the previous day. Communication with the RTL team about identified compliance issues and with the physical design team about upcoming scan reorder requirements are part of the daily routine.<\/span><\/p>\n

During the back-end phase, typical daily activities shift toward ATPG refinement, coverage gap investigation, and DFT timing verification review. Reviewing post-route timing reports for scan path violations, coordinating scan reordering with the physical design team, and preparing the test protocol documentation that the test team will use during bring-up are common activities.<\/span><\/p>\n

During the test program validation phase before tape-out, the DFT engineer’s<\/strong><\/a> focus is on confirming that the complete test program produces the required fault coverage, that the test protocol is correctly defined for the automated test equipment, and that all DFT sign-off criteria have been met. This phase often involves intensive collaboration with the verification team to confirm DFT structural correctness and with the test team to validate that the patterns can be correctly applied by the target test hardware.<\/span><\/p>\n

How the DFT Engineering Role Is Expected to Grow as Chip Complexity Increases<\/b><\/h3>\n

The DFT engineering role will become more demanding and more valuable as chip complexity continues to increase.<\/span><\/p>\n

Multi-die chiplet architectures present entirely new DFT challenges. Each chiplet requires its own DFT implementation, but testing the complete system also requires test infrastructure that operates across die boundaries through the inter-die interconnects. This requires DFT methodology that extends beyond single-die scan-based testing into heterogeneous integration test, an area where the methodology is still actively developing and where engineers who develop expertise early will be in a strong position.<\/span><\/p>\n

Advanced packaging technologies that integrate multiple chips in a single package require boundary scan and die interconnect test capabilities that add new layers of DFT complexity beyond what a single-die chip requires.<\/span><\/p>\n

AI and machine learning accelerators present DFT challenges related to the large, regular array structures that define their architecture. These structures require specialized BIST approaches rather than standard scan-based ATPG, and developing effective test methodology for them is an active area of DFT engineering research and development.<\/span><\/p>\n

Each of these trends creates demand for DFT engineers who can apply foundational methodology to new architectural contexts. The engineers who build strong DFT foundations through structured training now will be well positioned to develop this more advanced expertise as their careers progress, in a specialization where the demand consistently exceeds the supply of qualified engineers.<\/span><\/p>\n

 <\/p>\n","protected":false},"excerpt":{"rendered":"

What DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable Every chip that reaches a customer […]<\/p>\n","protected":false},"author":5,"featured_media":42353,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[1],"tags":[],"class_list":["post-42352","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-uncategorized"],"acf":[],"yoast_head":"\nWhat DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable<\/title>\n<meta name=\"description\" content=\"DFT engineers are essential to every chip that goes to fabrication. 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Learn what they do across the VLSI project lifecycle, how they collaborate with other teams, and why demand for this role keeps growing.\",\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\\\/\\\/chipedge.com\\\/resources\\\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\\\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\\\/#primaryimage\",\"url\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/wp-content\\\/uploads\\\/2026\\\/09\\\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg\",\"contentUrl\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/wp-content\\\/uploads\\\/2026\\\/09\\\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg\",\"width\":2560,\"height\":1707},{\"@type\":\"WebSite\",\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#website\",\"url\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/\",\"name\":\"chipedge\",\"description\":\"\",\"publisher\":{\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#organization\",\"name\":\"chipedge\",\"url\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#\\\/schema\\\/logo\\\/image\\\/\",\"url\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/wp-content\\\/uploads\\\/2025\\\/01\\\/logo.png\",\"contentUrl\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/wp-content\\\/uploads\\\/2025\\\/01\\\/logo.png\",\"width\":156,\"height\":40,\"caption\":\"chipedge\"},\"image\":{\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#\\\/schema\\\/logo\\\/image\\\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/#\\\/schema\\\/person\\\/92c7a497cf50673e1a70c70241776656\",\"name\":\"Bharath\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g\",\"url\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g\",\"contentUrl\":\"https:\\\/\\\/secure.gravatar.com\\\/avatar\\\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g\",\"caption\":\"Bharath\"},\"sameAs\":[\"http:\\\/\\\/www.chipedge.com\"],\"url\":\"https:\\\/\\\/chipedge.com\\\/resources\\\/author\\\/bharath\\\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"What DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable","description":"DFT engineers are essential to every chip that goes to fabrication. Learn what they do across the VLSI project lifecycle, how they collaborate with other teams, and why demand for this role keeps growing.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/","og_locale":"en_US","og_type":"article","og_title":"What DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable","og_description":"DFT engineers are essential to every chip that goes to fabrication. Learn what they do across the VLSI project lifecycle, how they collaborate with other teams, and why demand for this role keeps growing.","og_url":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/","og_site_name":"chipedge","article_published_time":"2026-09-21T09:20:25+00:00","og_image":[{"width":2560,"height":1707,"url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/09\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg","type":"image\/jpeg"}],"author":"Bharath","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Bharath","Est. reading time":"12 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":["Article","BlogPosting"],"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#article","isPartOf":{"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/"},"author":{"name":"Bharath","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/person\/92c7a497cf50673e1a70c70241776656"},"headline":"No title","datePublished":"2026-09-21T09:20:25+00:00","mainEntityOfPage":{"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/"},"wordCount":2555,"commentCount":0,"publisher":{"@id":"https:\/\/chipedge.com\/resources\/#organization"},"image":{"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#primaryimage"},"thumbnailUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/09\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg","inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/","url":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/","name":"What DFT Engineers Actually Do in VLSI Projects and Why Their Role Is Indispensable","isPartOf":{"@id":"https:\/\/chipedge.com\/resources\/#website"},"primaryImageOfPage":{"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#primaryimage"},"image":{"@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#primaryimage"},"thumbnailUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/09\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg","datePublished":"2026-09-21T09:20:25+00:00","description":"DFT engineers are essential to every chip that goes to fabrication. Learn what they do across the VLSI project lifecycle, how they collaborate with other teams, and why demand for this role keeps growing.","inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/chipedge.com\/resources\/dft-in-vlsi-what-engineers-do-why-role-is-indispensable\/#primaryimage","url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/09\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg","contentUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2026\/09\/8c34414bbbb26fda4e8721c7243776a0a326e326-scaled.jpg","width":2560,"height":1707},{"@type":"WebSite","@id":"https:\/\/chipedge.com\/resources\/#website","url":"https:\/\/chipedge.com\/resources\/","name":"chipedge","description":"","publisher":{"@id":"https:\/\/chipedge.com\/resources\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/chipedge.com\/resources\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/chipedge.com\/resources\/#organization","name":"chipedge","url":"https:\/\/chipedge.com\/resources\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/","url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png","contentUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png","width":156,"height":40,"caption":"chipedge"},"image":{"@id":"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/person\/92c7a497cf50673e1a70c70241776656","name":"Bharath","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/secure.gravatar.com\/avatar\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/bd8911ea84495e1fb12b4fb607c4a8205c01edaf4ee976d70adb31894e427079?s=96&d=mm&r=g","caption":"Bharath"},"sameAs":["http:\/\/www.chipedge.com"],"url":"https:\/\/chipedge.com\/resources\/author\/bharath\/"}]}},"_links":{"self":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts\/42352","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/comments?post=42352"}],"version-history":[{"count":1,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts\/42352\/revisions"}],"predecessor-version":[{"id":42354,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts\/42352\/revisions\/42354"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/media\/42353"}],"wp:attachment":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/media?parent=42352"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/categories?post=42352"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/tags?post=42352"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}