{"id":41672,"date":"2026-05-08T07:03:19","date_gmt":"2026-05-08T07:03:19","guid":{"rendered":"https:\/\/chipedge.com\/resources\/?p=41672"},"modified":"2026-06-08T07:17:48","modified_gmt":"2026-06-08T07:17:48","slug":"physical-design-interview-questions-what-interviews-really-feel-like","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/physical-design-interview-questions-what-interviews-really-feel-like\/","title":{"rendered":"Physical Design Interview Questions: What Interviews Really Feel Like"},"content":{"rendered":"<p><span style=\"font-weight: 400;\">Physical design interviews usually become technical very quickly.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">One minute you\u2019re talking about your project. The next minute someone asks why hold violations suddenly increased after CTS or what you\u2019d check first if routing congestion appears even at moderate utilization.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That shift catches a lot of people off guard.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Most interviewers are not trying to hear textbook definitions word for word. They want to know whether you actually understand what happens inside a backend flow when something breaks. Because eventually, something always breaks.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">And honestly, that\u2019s normal in physical design.<\/span><\/p>\n<h2><b>What Interviewers Usually Want to See<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">Freshers often assume interviews are about memorizing commands or definitions. They\u2019re not.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Interviewers care more about your reasoning.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">If you explain <\/span><i><span style=\"font-weight: 400;\">why<\/span><\/i><span style=\"font-weight: 400;\"> placement affects congestion or <\/span><i><span style=\"font-weight: 400;\">why<\/span><\/i><span style=\"font-weight: 400;\"> skew changes after CTS, the discussion becomes much stronger immediately. Even if your wording isn\u2019t perfect, showing real understanding matters more.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">A candidate who understands tradeoffs generally performs better than someone giving memorized answers.<\/span><\/p>\n<h2><b>Floorplanning Questions<\/b><\/h2>\n<h3><b>What is floorplanning? Why is it important?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Floorplanning is basically the starting point of physical implementation.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">This is where macro locations, IO placement, power planning, and core dimensions get decided. A weak floorplan creates problems everywhere later \u2014 congestion, routing difficulty, timing failures, sometimes even power issues.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">One thing students usually underestimate is how early decisions affect everything downstream.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">A slightly bad macro placement can keep hurting the design all the way until signoff.<\/span><\/p>\n<h2><b>What affects macro placement?<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">Usually a combination of:<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Timing requirements<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Routing channels<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Power structure<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">IO proximity<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Congestion risk<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">Macros that communicate heavily are generally placed closer together. Otherwise wirelength increases and timing becomes harder to close.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">But in real projects, constraints often conflict with each other. That\u2019s where engineering judgment comes in.<\/span><\/p>\n<h2><b>What is utilization in floorplanning?<\/b><\/h2>\n<p><span style=\"font-weight: 400;\">Utilization refers to how much core area is occupied by cells and macros.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Higher utilization sounds efficient initially, but aggressive utilization creates routing congestion very quickly. Most designs stay within a safer range to leave room for buffers, CTS optimization, and routing resources.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Students often focus only on area reduction. Backend engineers usually think ahead about routability too.<\/span><\/p>\n<h2><b>Placement Questions<\/b><\/h2>\n<h3><b>Difference between global placement and detail placement<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Global placement spreads cells roughly across the chip while trying to reduce wirelength.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Detail placement comes later and legalizes the placement properly according to design rules.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">You can think of global placement as rough organization and detail placement as cleanup plus optimization.<\/span><\/p>\n<h3><b>How does placement affect congestion?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Placement decisions directly influence routing demand.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">If too many highly connected cells sit inside one area, routing resources get exhausted there. Congestion hotspots appear, and later stages become painful.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">A lot of routing problems actually begin during placement, not routing itself.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That connection is important during interviews.<\/span><\/p>\n<h3><b>What is timing-driven placement?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Timing-driven placement prioritizes critical timing paths during optimization.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Cells on important paths get positioned more carefully to reduce delay. Without timing-driven optimization, placement may look clean physically but still fail timing badly.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Most modern high-performance designs rely heavily on timing-aware optimization throughout the flow.<\/span><\/p>\n<h2><b>CTS Questions<\/b><\/h2>\n<h3><b>Why is CTS done after placement?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Because clock tree design depends on the physical locations of flip-flops.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Without placement information, the tool has no idea how to balance clock latency properly. If CTS happened before placement, the clock tree would become inaccurate once cells moved.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That\u2019s usually the simplest way to explain it in interviews.<\/span><\/p>\n<h3><b>What is clock skew?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Clock skew is the difference in clock arrival times between flip-flops.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Too much skew creates setup or hold timing problems. Controlled skew can sometimes help timing closure, though.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That\u2019s where useful skew comes into the discussion.<\/span><\/p>\n<h3><b>Useful skew vs harmful skew<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Useful skew is intentionally introduced to improve timing on difficult paths.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Harmful skew happens unintentionally and creates violations instead of helping.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Interviewers ask this because they want to see whether you understand skew as an optimization parameter, not just a timing problem.<\/span><\/p>\n<h2><b>Routing Questions<\/b><\/h2>\n<h3><b>Difference between global routing and detailed routing<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Global routing estimates routing resources and identifies congestion regions early.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Detailed routing creates the actual wire paths and vias while following strict design rules.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Global routing is more predictive. Detailed routing is implementation-focused.<\/span><\/p>\n<h3><b>What causes routing congestion?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Usually some mix of:<\/span><\/p>\n<ul>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Dense placement<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Poor floorplanning<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Macro blockage<\/span><\/li>\n<li style=\"font-weight: 400;\" aria-level=\"1\"><span style=\"font-weight: 400;\">Excessive connectivity in one region<\/span><\/li>\n<\/ul>\n<p><span style=\"font-weight: 400;\">Congestion rarely appears randomly. There\u2019s almost always an upstream reason.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That\u2019s something experienced interviewers like hearing.<\/span><\/p>\n<h3><b>What is antenna effect?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">During fabrication, long metal wires can accumulate charge and damage gate oxides.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Antenna violations are fixed using techniques like antenna diodes, jumper insertion, or routing changes.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Most people memorize the definition. Fewer people explain <\/span><i><span style=\"font-weight: 400;\">why<\/span><\/i><span style=\"font-weight: 400;\"> it matters physically.<\/span><\/p>\n<h2><b>STA Questions<\/b><\/h2>\n<h3><b>What is static timing analysis?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">STA checks timing paths mathematically without running dynamic simulation.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">It analyzes whether signals can propagate correctly under different conditions and timing corners.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Without STA, validating large ASIC designs would become almost impossible practically.<\/span><\/p>\n<h3><b>Difference between setup and hold violations<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Setup violation means data arrives too late.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Hold violation means data changes too early.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Freshers usually find hold fixing more confusing because the solution often involves intentionally adding delay rather than removing it.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">That feels counterintuitive initially.<\/span><\/p>\n<h3><b>What are timing corners?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Different process, voltage, and temperature conditions affect circuit speed differently.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Designs must work reliably across all required corners, not just one ideal condition.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Slow corners usually stress setup timing. Fast corners expose hold issues more aggressively.<\/span><\/p>\n<h2><b>Physical Verification Questions<\/b><\/h2>\n<h3><b>What is DRC?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">DRC checks whether the layout follows manufacturing rules like spacing, width, and enclosure constraints.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Passing DRC means the layout is manufacturable geometrically.<\/span><\/p>\n<h3><b>What is LVS?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">LVS compares the physical layout connectivity against the original schematic or netlist.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">A clean LVS confirms the implemented layout matches the intended design electrically.<\/span><\/p>\n<h2><b>Questions That Usually Surprise Candidates<\/b><\/h2>\n<h3><b>What if timing closes at block level but fails at top level?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">This often points toward interface timing or top-level constraint issues.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Clock definitions, IO constraints, CDC paths, or integration-level timing assumptions become common suspects.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">A lot of real debugging starts at integration boundaries.<\/span><\/p>\n<h3><b>What if routing fails even with reasonable utilization?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">That usually suggests local congestion rather than overall utilization problems.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Congestion maps become important here because average utilization numbers sometimes hide severe hotspots.<\/span><\/p>\n<h3><b>What if hold violations appear after CTS?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Post-CTS hold violations are commonly caused by skew changes introduced by the clock tree.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">The clock path behavior changes after CTS, which affects launch and capture timing relationships.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">This is one of those issues students understand much better after seeing it happen in tools directly.<\/span><\/p>\n<h3><b>How to Prepare Properly<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Reading <span data-sheets-root=\"1\">physical design <\/span>interview questions helps. But <a href=\"https:\/\/chipedge.com\/physical-design\">physical design<\/a> becomes easier only after working through actual flows.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Running placement, analyzing timing reports, debugging congestion, fixing violations \u2014 that practical exposure changes how you answer technical questions.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Interviewers notice immediately when someone has worked with tools instead of only reading theory.<\/span><\/p>\n<p><span style=\"font-weight: 400;\">Even small project experience helps.<\/span><\/p>\n<h2><b>FAQ<\/b><\/h2>\n<h3><b>What topics are asked in physical design interviews?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Floor<\/span><span style=\"font-weight: 400;\">powrplan<\/span><span style=\"font-weight: 400;\">,<\/span><span style=\"font-weight: 400;\"> placement, CTS, routing, STA, congestion, DRC, LVS, and timing closure are commonly discussed.<\/span><\/p>\n<h3><b>Are fresher interviews different from experienced-level interviews?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Yes. Freshers are usually tested on fundamentals and reasoning, while experienced engineers discuss real implementation challenges and project decisions.<\/span><\/p>\n<h3><b>Which tools are commonly expected?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">ICC2, Innovus, PrimeTime, and basic Tcl scripting knowledge are commonly expected in backend interviews.<\/span><\/p>\n<h3><b>How important is STA knowledge?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Very important. Timing analysis questions appear in almost every physical design interview.<\/span><\/p>\n<h3><b>Is scripting necessary for backend roles?<\/b><\/h3>\n<p><span style=\"font-weight: 400;\">Basic Tcl scripting is extremely common in physical design environments and helps automate flows and report analysis.<\/span><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Physical design interviews usually become technical very quickly. One minute you\u2019re talking about your project. The next minute someone asks [&hellip;]<\/p>\n","protected":false},"author":5,"featured_media":41673,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"default","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"default","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"set","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center 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