{"id":27450,"date":"2023-11-07T07:33:10","date_gmt":"2023-11-07T07:33:10","guid":{"rendered":"https:\/\/chipedge.com\/?p=27450"},"modified":"2023-11-07T07:33:10","modified_gmt":"2023-11-07T07:33:10","slug":"how-to-meet-coverage-criteria-and-coverage-goals","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/how-to-meet-coverage-criteria-and-coverage-goals\/","title":{"rendered":"How to Meet Coverage Criteria and Coverage Goals"},"content":{"rendered":"\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

In the world of VLSI design, meeting coverage criteria is of paramount importance to ensure the functionality, reliability, and performance of integrated circuits. Coverage criteria in the context of VLSI design refer to the specific aspects of the design that need to be tested to guarantee the desired quality level. These criteria play a crucial role in validating and verifying complex VLSI designs.\u00a0<\/span><\/p>

Understanding the Coverage Criteria<\/span><\/h2>

For most design verification engineers, achieving complete coverage is the source of many restless nights. It involves the often tedious task of subjecting your Design Under Test (DUT) to a seemingly endless stream of stimuli, all in line with the coverage criteria defined in your verification plan. The goal is to thoroughly scrutinize your design for potential issues, but how can you be confident that you have unearthed any hidden bugs lurking deep within your design?<\/span><\/p>

The ideal scenario would be to have a tool that guarantees 100% coverage. <\/span>
<\/span>
<\/span>Hence, coverage criteria in VLSI encompass a range of metrics and measurements that assess the comprehensiveness of the testing process. They aim to ensure that all aspects of the <\/span>design verification in VLSI<\/span><\/a>, including structural, functional, and temporal characteristics, are thoroughly verified.<\/span><\/p>

\"Self<\/a><\/p>

Identifying Coverage Goals<\/span><\/h2>

Coverage holds a significant role in design verification, as it provides a detailed breakdown of the issues that have been tested as opposed to those that remain untested. While having comprehensive coverage criteria or metrics for all peripherals is desirable, it introduces additional overhead to simulators, which can significantly impede simulation speed. There has always been a trade-off between coverage and simulation speed, making it essential to assess the design’s complexity before pinpointing coverage targets.\u00a0<\/span><\/p>

Achieving the desired coverage can be realized through assertions or coverage metrics, but regardless of the method, the definition of coverage points assumes a critical role. For SOC verification, it is advisable to include coverage for aspects such as interconnectivity, interrupt handling, system-specific behaviors like power-saving features, recovery sequences, and the management of resets and clock functionality, as well as the system buses.<\/span><\/p>

Here are a few <\/span>job prospects in ASIC Design Verification <\/span><\/a>in VLSI.<\/span><\/p>

Types of Coverage Criteria and Coverage Goals\u00a0<\/span><\/h2>

The main types of coverage criteria in VLSI include:<\/span><\/p>

Code Coverage<\/span><\/h3>

Code coverage assesses the execution of the actual RTL (Register-Transfer Level) code, necessitating the presence of the RTL code before any code coverage analysis can occur. Collecting code coverage data, including statement and branch coverage, state coverage, and state transition coverage, is largely automated. Code coverage offers a quantitative measure of the DUT’s code execution.<\/span><\/p>

Functional Coverage<\/span><\/h3>

In contrast, functional coverage endeavors to determine whether the features outlined in the verification plan have genuinely been executed by the DUT. Identifying the features to be assessed requires brainstorming based on the specification and design implementation, forming the foundation for the verification plan. Consequently, functional coverage provides a qualitative measure of the DUT’s code execution. The extent to which these features need to be exercised by functional coverage depends on the diligence and comprehensiveness of the individuals crafting the verification plan.<\/span><\/p>

Know more about <\/span>the role of design verification in VLSI design<\/span><\/a>.\u00a0\u00a0<\/span><\/p>

\"weekend<\/a><\/p>

How to Meet Coverage Criteria and Coverage Goals in VLSI Design?<\/span><\/h2>