{"id":26632,"date":"2023-10-17T12:40:47","date_gmt":"2023-10-17T12:40:47","guid":{"rendered":"https:\/\/chipedge.com\/?p=26632"},"modified":"2023-10-17T12:40:47","modified_gmt":"2023-10-17T12:40:47","slug":"understanding-the-intricacies-of-soc-design-flow","status":"publish","type":"post","link":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/","title":{"rendered":"Understanding The Intricacies of SOC Design Flow"},"content":{"rendered":"\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t\t
\n\t\t\t
\n\t\t\t\t\t\t
\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t

In the rapidly evolving world of technology, the System-on-Chip(SoC) design has emerged as the foundation for many electronic devices, ranging from smartphones, tablets, and IoT gadgets to automotive systems. The road to success in SoC design necessitates a profound grasp of the design process- a systematic approach that guarantees streamlined and error-free development. In this article, let us explore the intricacies of the SoC design flow, elucidating the essential stages and recommended strategies that engineers and designers should adhere to when striving to develop state-of-the-art SoCs.<\/span><\/p>

Phases of SoC Design Flow<\/span><\/h2>

The SOC design flow begins with a clear understanding of the project’s objectives. This initial phase involves brainstorming and defining the system’s requirements and functionalities. Key considerations include the target application, power efficiency, performance, and connectivity. Collaboration between hardware and software teams is crucial to ensure that both aspects align with the desired outcomes. The SoC design landscape can be classified into three distinct scenarios:<\/span><\/p>

ASIC Vendor Design<\/span><\/h3>

This entails the complete design and fabrication of all chip components by an ASIC vendor.<\/span><\/p>

\"Job-Oriented<\/a><\/p>

Integrated Design<\/span><\/h3>

This involves the design by an ASIC vendor, where not all components are internally designed but rather incorporate cores sourced from external providers, such as core\/IP vendors or foundries.<\/span><\/p>

Desktop Design<\/span><\/h3>

This encompasses the design undertaken by fabless companies, predominantly relying on externally sourced cores from various providers, including IP companies, EDA companies, design services companies, or foundries.<\/span><\/p>

Enrolling in a <\/span>VLSI course <\/span><\/a>will offer you valuable insights and hands-on experience in this field, whether you are a beginner or aiming to elevate your expertise.<\/span><\/p>

Understanding Conceptualization and Specification of SoC Design Flow<\/span><\/h2>

SoC design techniques build upon the foundations of ASIC design methods. Therefore, any system design style proposed for SoCs needs to align seamlessly with ASIC design flows. In practice, an effective SoC design style should harmonize effortlessly with the existing ASIC design flow, sparing the SoC design team from the need to acquire and adapt to entirely new design tools.\u00a0<\/span><\/p>

The SOC design process encompasses several crucial stages:<\/span><\/p>

Architecture Design<\/span><\/h3>

Following the establishment of specifications, architects create a high-level design outlining CPU core arrangement, memory hierarchy, buses, and interfaces. Choices made here significantly impact performance, power efficiency, and overall functionality.<\/span><\/p>

IP Selection and Integration<\/span><\/h3>

SOC designs often incorporate diverse intellectual property (IP) blocks like CPUs, GPUs, and memory controllers. Engineers must meticulously select and integrate these IPs while considering compatibility, licensing, and performance.<\/span><\/p>

RTL Design and Verification<\/span><\/h3>

At the Register Transfer Level (RTL), engineers craft code specifying component behavior and connectivity. Rigorous verification, including simulation and formal checks, ensures compliance with specifications and error-free design.<\/span><\/p>

Synthesis and Physical Design<\/span><\/h3>

RTL undergoes synthesis, transforming it into a gate-level netlist. Physical design, includes floor planning, placement, cts and routing, is vital for meeting performance, power, and area targets.<\/span><\/p>

Functional Verification<\/span><\/h3>

Comprehensive testing confirms SOC functionality under various conditions, covering software, firmware, and industry standards.<\/span><\/p>

\"weekend<\/a><\/p>

Tape-out<\/span><\/h3>

The final design is sent to a fabrication facility for manufacturing, requiring meticulous error prevention due to the high costs associated with post-tape-out corrections.<\/span><\/p>

Here are a few <\/span>SoC interview questions<\/span><\/a> for you to get started.<\/span><\/p>

Post-silicon Validation<\/span><\/h3>

Fabricated chips undergo hardware testing and debugging, revealing subtle issues not apparent during pre-silicon verification.<\/span><\/p>

Software Development<\/span><\/h3>

Simultaneously, software development includes creating device drivers, firmware, and software stacks for seamless interaction with operating systems and applications.<\/span><\/p>

Mass Production<\/span><\/h3>

With successful validation, mass production begins, producing a large quantity of chips for integration into electronic devices and systems.<\/span><\/p>

Conclusion<\/span><\/h2>

The SOC design flow is a complex and multifaceted process that requires meticulous planning, collaboration, and attention to detail. So are you ready to master the intricate world of SoC design flow? Chipedge, your trusted <\/span>VLSI training institute in Bangalore<\/span><\/a>, is here to guide you. Our comprehensive <\/span>VLSI online course<\/span><\/a> is designed to equip you with the skills and knowledge you need to excel in this dynamic field. Join the ranks of successful VLSI professionals by enrolling in our program today. Don’t miss this opportunity to boost your VLSI career and embark on your journey today!<\/span><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t

\n\t\t\t\t
\n\t\t\t\t\t\t\t\t\t
\n\t\t\t\t\t\n\t\t\t\t\t\t\n\t\t\t\t\t\t\t\t\tExplore Self Paced VLSI Courses<\/span>\n\t\t\t\t\t<\/span>\n\t\t\t\t\t<\/a>\n\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<\/div>\n\t\t","protected":false},"excerpt":{"rendered":"

In the rapidly evolving world of technology, the System-on-Chip(SoC) design has emerged as the foundation for many electronic devices, ranging […]<\/p>\n","protected":false},"author":19,"featured_media":26633,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"site-sidebar-layout":"default","site-content-layout":"","ast-site-content-layout":"","site-content-style":"default","site-sidebar-style":"default","ast-global-header-display":"","ast-banner-title-visibility":"","ast-main-header-display":"","ast-hfb-above-header-display":"","ast-hfb-below-header-display":"","ast-hfb-mobile-header-display":"","site-post-title":"","ast-breadcrumbs-content":"","ast-featured-img":"","footer-sml-layout":"","theme-transparent-header-meta":"","adv-header-id-meta":"","stick-header-meta":"","header-above-stick-meta":"","header-main-stick-meta":"","header-below-stick-meta":"","astra-migrate-meta-layouts":"default","ast-page-background-enabled":"default","ast-page-background-meta":{"desktop":{"background-color":"var(--ast-global-color-4)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"ast-content-background-meta":{"desktop":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"tablet":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""},"mobile":{"background-color":"var(--ast-global-color-5)","background-image":"","background-repeat":"repeat","background-position":"center center","background-size":"auto","background-attachment":"scroll","background-type":"","background-media":"","overlay-type":"","overlay-color":"","overlay-opacity":"","overlay-gradient":""}},"footnotes":""},"categories":[15],"tags":[35,40,18],"class_list":["post-26632","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-soc-design","tag-aisc-design-verification","tag-best-vlsi-training","tag-best-vlsi-training-institute-in-bangalore"],"acf":[],"yoast_head":"\nUnderstanding The Intricacies of SOC Design Flow<\/title>\n<meta name=\"description\" content=\"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.\" \/>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\" \/>\n<meta property=\"og:locale\" content=\"en_US\" \/>\n<meta property=\"og:type\" content=\"article\" \/>\n<meta property=\"og:title\" content=\"Understanding The Intricacies of SOC Design Flow\" \/>\n<meta property=\"og:description\" content=\"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.\" \/>\n<meta property=\"og:url\" content=\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\" \/>\n<meta property=\"og:site_name\" content=\"chipedge\" \/>\n<meta property=\"article:published_time\" content=\"2023-10-17T12:40:47+00:00\" \/>\n<meta property=\"og:image\" content=\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp\" \/>\n\t<meta property=\"og:image:width\" content=\"1486\" \/>\n\t<meta property=\"og:image:height\" content=\"992\" \/>\n\t<meta property=\"og:image:type\" content=\"image\/webp\" \/>\n<meta name=\"author\" content=\"Raghav M\" \/>\n<meta name=\"twitter:card\" content=\"summary_large_image\" \/>\n<meta name=\"twitter:label1\" content=\"Written by\" \/>\n\t<meta name=\"twitter:data1\" content=\"Raghav M\" \/>\n\t<meta name=\"twitter:label2\" content=\"Est. reading time\" \/>\n\t<meta name=\"twitter:data2\" content=\"4 minutes\" \/>\n<script type=\"application\/ld+json\" class=\"yoast-schema-graph\">{\"@context\":\"https:\/\/schema.org\",\"@graph\":[{\"@type\":[\"Article\",\"BlogPosting\"],\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#article\",\"isPartOf\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\"},\"author\":{\"name\":\"Raghav M\",\"@id\":\"https:\/\/chipedge.com\/resources\/#\/schema\/person\/9231638c6d58d6e14efb4d945088f703\"},\"headline\":\"Understanding The Intricacies of SOC Design Flow\",\"datePublished\":\"2023-10-17T12:40:47+00:00\",\"mainEntityOfPage\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\"},\"wordCount\":691,\"commentCount\":0,\"publisher\":{\"@id\":\"https:\/\/chipedge.com\/resources\/#organization\"},\"image\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp\",\"keywords\":[\"aisc design verification\",\"best vlsi training\",\"Best VLSI Training Institute in Bangalore\"],\"articleSection\":[\"SOC Design\"],\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"CommentAction\",\"name\":\"Comment\",\"target\":[\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#respond\"]}]},{\"@type\":\"WebPage\",\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\",\"url\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\",\"name\":\"Understanding The Intricacies of SOC Design Flow\",\"isPartOf\":{\"@id\":\"https:\/\/chipedge.com\/resources\/#website\"},\"primaryImageOfPage\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage\"},\"image\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage\"},\"thumbnailUrl\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp\",\"datePublished\":\"2023-10-17T12:40:47+00:00\",\"description\":\"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.\",\"breadcrumb\":{\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#breadcrumb\"},\"inLanguage\":\"en-US\",\"potentialAction\":[{\"@type\":\"ReadAction\",\"target\":[\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/\"]}]},{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage\",\"url\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp\",\"contentUrl\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp\",\"width\":1486,\"height\":992},{\"@type\":\"BreadcrumbList\",\"@id\":\"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#breadcrumb\",\"itemListElement\":[{\"@type\":\"ListItem\",\"position\":1,\"name\":\"Home\",\"item\":\"https:\/\/chipedge.com\/resources\/\"},{\"@type\":\"ListItem\",\"position\":2,\"name\":\"Understanding The Intricacies of SOC Design Flow\"}]},{\"@type\":\"WebSite\",\"@id\":\"https:\/\/chipedge.com\/resources\/#website\",\"url\":\"https:\/\/chipedge.com\/resources\/\",\"name\":\"chipedge\",\"description\":\"\",\"publisher\":{\"@id\":\"https:\/\/chipedge.com\/resources\/#organization\"},\"potentialAction\":[{\"@type\":\"SearchAction\",\"target\":{\"@type\":\"EntryPoint\",\"urlTemplate\":\"https:\/\/chipedge.com\/resources\/?s={search_term_string}\"},\"query-input\":{\"@type\":\"PropertyValueSpecification\",\"valueRequired\":true,\"valueName\":\"search_term_string\"}}],\"inLanguage\":\"en-US\"},{\"@type\":\"Organization\",\"@id\":\"https:\/\/chipedge.com\/resources\/#organization\",\"name\":\"chipedge\",\"url\":\"https:\/\/chipedge.com\/resources\/\",\"logo\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/\",\"url\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png\",\"contentUrl\":\"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png\",\"width\":156,\"height\":40,\"caption\":\"chipedge\"},\"image\":{\"@id\":\"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/\"}},{\"@type\":\"Person\",\"@id\":\"https:\/\/chipedge.com\/resources\/#\/schema\/person\/9231638c6d58d6e14efb4d945088f703\",\"name\":\"Raghav M\",\"image\":{\"@type\":\"ImageObject\",\"inLanguage\":\"en-US\",\"@id\":\"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g\",\"url\":\"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g\",\"contentUrl\":\"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g\",\"caption\":\"Raghav M\"},\"url\":\"https:\/\/chipedge.com\/resources\/author\/raghav-m\/\"}]}<\/script>\n<!-- \/ Yoast SEO plugin. -->","yoast_head_json":{"title":"Understanding The Intricacies of SOC Design Flow","description":"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.","robots":{"index":"index","follow":"follow","max-snippet":"max-snippet:-1","max-image-preview":"max-image-preview:large","max-video-preview":"max-video-preview:-1"},"canonical":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/","og_locale":"en_US","og_type":"article","og_title":"Understanding The Intricacies of SOC Design Flow","og_description":"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.","og_url":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/","og_site_name":"chipedge","article_published_time":"2023-10-17T12:40:47+00:00","og_image":[{"width":1486,"height":992,"url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp","type":"image\/webp"}],"author":"Raghav M","twitter_card":"summary_large_image","twitter_misc":{"Written by":"Raghav M","Est. reading time":"4 minutes"},"schema":{"@context":"https:\/\/schema.org","@graph":[{"@type":["Article","BlogPosting"],"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#article","isPartOf":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/"},"author":{"name":"Raghav M","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/person\/9231638c6d58d6e14efb4d945088f703"},"headline":"Understanding The Intricacies of SOC Design Flow","datePublished":"2023-10-17T12:40:47+00:00","mainEntityOfPage":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/"},"wordCount":691,"commentCount":0,"publisher":{"@id":"https:\/\/chipedge.com\/resources\/#organization"},"image":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage"},"thumbnailUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp","keywords":["aisc design verification","best vlsi training","Best VLSI Training Institute in Bangalore"],"articleSection":["SOC Design"],"inLanguage":"en-US","potentialAction":[{"@type":"CommentAction","name":"Comment","target":["https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#respond"]}]},{"@type":"WebPage","@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/","url":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/","name":"Understanding The Intricacies of SOC Design Flow","isPartOf":{"@id":"https:\/\/chipedge.com\/resources\/#website"},"primaryImageOfPage":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage"},"image":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage"},"thumbnailUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp","datePublished":"2023-10-17T12:40:47+00:00","description":"Explore the intricate world of SoC design flow and uncover the critical phases of the design process in the article below.","breadcrumb":{"@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#breadcrumb"},"inLanguage":"en-US","potentialAction":[{"@type":"ReadAction","target":["https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/"]}]},{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#primaryimage","url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp","contentUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2023\/10\/man-repairing-cpu-with-screwdriver_11zon.webp","width":1486,"height":992},{"@type":"BreadcrumbList","@id":"https:\/\/chipedge.com\/resources\/understanding-the-intricacies-of-soc-design-flow\/#breadcrumb","itemListElement":[{"@type":"ListItem","position":1,"name":"Home","item":"https:\/\/chipedge.com\/resources\/"},{"@type":"ListItem","position":2,"name":"Understanding The Intricacies of SOC Design Flow"}]},{"@type":"WebSite","@id":"https:\/\/chipedge.com\/resources\/#website","url":"https:\/\/chipedge.com\/resources\/","name":"chipedge","description":"","publisher":{"@id":"https:\/\/chipedge.com\/resources\/#organization"},"potentialAction":[{"@type":"SearchAction","target":{"@type":"EntryPoint","urlTemplate":"https:\/\/chipedge.com\/resources\/?s={search_term_string}"},"query-input":{"@type":"PropertyValueSpecification","valueRequired":true,"valueName":"search_term_string"}}],"inLanguage":"en-US"},{"@type":"Organization","@id":"https:\/\/chipedge.com\/resources\/#organization","name":"chipedge","url":"https:\/\/chipedge.com\/resources\/","logo":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/","url":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png","contentUrl":"https:\/\/chipedge.com\/resources\/wp-content\/uploads\/2025\/01\/logo.png","width":156,"height":40,"caption":"chipedge"},"image":{"@id":"https:\/\/chipedge.com\/resources\/#\/schema\/logo\/image\/"}},{"@type":"Person","@id":"https:\/\/chipedge.com\/resources\/#\/schema\/person\/9231638c6d58d6e14efb4d945088f703","name":"Raghav M","image":{"@type":"ImageObject","inLanguage":"en-US","@id":"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g","url":"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g","contentUrl":"https:\/\/secure.gravatar.com\/avatar\/71a0351b9fcad7547813603974b10f0dd7d323aaa02928fe7fb5a2ac8a51ea1d?s=96&d=mm&r=g","caption":"Raghav M"},"url":"https:\/\/chipedge.com\/resources\/author\/raghav-m\/"}]}},"_links":{"self":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts\/26632","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/users\/19"}],"replies":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/comments?post=26632"}],"version-history":[{"count":0,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/posts\/26632\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/media\/26633"}],"wp:attachment":[{"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/media?parent=26632"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/categories?post=26632"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/chipedge.com\/resources\/wp-json\/wp\/v2\/tags?post=26632"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}